Re: [Patch V3 4/8] dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding

Reviewed-by: JC Kuo Thanks, JC On 5/16/19 2:39 PM, Nagarjuna Kristam wrote: Add device-tree binding documentation for the XUSB device mode controller present on Tegra210 SoC. This controller supports the USB 3.0 specification. Signed-off-by: Nagarjuna Kristam --- .../devicetree/bindings

Re: [Patch V3 5/8] arm64: tegra: Add xudc node for Tegra210

Reviewed-by: JC Kuo Thanks, JC On 5/16/19 2:39 PM, Nagarjuna Kristam wrote: Tegra210 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT support for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam --- arch/arm64/boot/dts/nvidia/tegra210.dtsi

Re: [Patch V3 6/8] arm64: tegra: Enable xudc on Jetson TX1

Reviewed-by: JC Kuo Thanks, JC On 5/16/19 2:39 PM, Nagarjuna Kristam wrote: Enable XUSB device mode driver for USB0 slot on Jetson TX1. Signed-off-by: Nagarjuna Kristam --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 14 ++ 1 file changed, 14 insertions(+) diff --git a

[PATCH 0/8] Tegra XHCI controller ELPG support

. JC Kuo (8): clk: tegra: Add PLLE HW power sequencer control clk: tegra: don't enable PLLE HW sequencer at init phy: tegra: xusb: t210: rearrange UPHY init phy: tegra: xusb: add sleepwalk and suspend/resume soc/tegra: pmc: support T210 USB 2.0 Sleepwalk phy: tegra: xusb: t210: support

[PATCH 4/8] phy: tegra: xusb: add sleepwalk and suspend/resume

This commit adds sleepwalk/wake and suspend/resume interfaces to Tegra XUSB PHY driver. Signed-off-by: JC Kuo --- drivers/phy/tegra/xusb.c | 78 ++ drivers/phy/tegra/xusb.h | 8 include/linux/phy/tegra/xusb.h | 12 ++ 3 files changed, 98

[PATCH 1/8] clk: tegra: Add PLLE HW power sequencer control

PLLE hardware sequencer has been enabled or not. Signed-off-by: JC Kuo --- drivers/clk/tegra/clk-tegra210.c | 45 include/linux/clk/tegra.h| 2 ++ 2 files changed, 47 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra

[PATCH 3/8] phy: tegra: xusb: t210: rearrange UPHY init

will be programmed at LP0 exit. Signed-off-by: JC Kuo --- drivers/phy/tegra/xusb-tegra210.c | 443 ++ drivers/phy/tegra/xusb.c | 2 +- drivers/phy/tegra/xusb.h | 2 + 3 files changed, 264 insertions(+), 183 deletions(-) diff --git a/drivers/phy

[PATCH 2/8] clk: tegra: don't enable PLLE HW sequencer at init

PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo --- drivers/clk/tegra/clk-pll.c | 12 -

[PATCH 8/8] xhci: tegra: enable ELPG for runtime/system PM

This commit enables XUSB host controller ELPG for runtime and system power management. NEED CLEANUP. Signed-off-by: JC Kuo --- drivers/usb/host/xhci-tegra.c | 802 -- 1 file changed, 671 insertions(+), 131 deletions(-) diff --git a/drivers/usb/host/xhci-tegra.c

[PATCH 7/8] arm64: tegra: add Tegra210 XUSB PADCTL irq

XUSB PADCTL interrupt will be raised when USB wake event happens. This is required for supporting XUSB host controller ELPG. Signed-off-by: JC Kuo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia

[PATCH 6/8] phy: tegra: xusb: t210: support wake and sleepwalk

This commit implements Tegra210 XUSB PADCTL wake and sleepwalk routines. Signed-off-by: JC Kuo --- drivers/phy/tegra/xusb-tegra210.c | 574 -- 1 file changed, 548 insertions(+), 26 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb

[PATCH 5/8] soc/tegra: pmc: support T210 USB 2.0 Sleepwalk

resume signal accordingly till XUSB host controller is bring out of ELPG. Signed-off-by: JC Kuo --- drivers/soc/tegra/pmc.c | 462 include/soc/tegra/pmc.h | 13 ++ 2 files changed, 475 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc

Re: [PATCH 8/8] xhci: tegra: enable ELPG for runtime/system PM

Hi Greg, Code cleanup was done but I forgot the "NEED CLEANUP" in the commit comment. Sorry for that. I will wait for review comments to come and fix the commit message together with code improvements. Thanks, JC On 6/18/19 2:33 PM, Greg KH wrote: > On Fri, Jun 14, 2019 at 03:48:2

[PATCH] usb: storage: skip only when uas driver is loaded

er is already loaded to make sure the device will at least work with Bulk protocol. Signed-off-by: JC Kuo --- drivers/usb/core/driver.c | 1 + drivers/usb/storage/usb.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c

Re: [PATCH] usb: storage: skip only when uas driver is loaded

On 7/1/19 4:52 PM, Greg KH wrote: > On Mon, Jul 01, 2019 at 04:48:48PM +0800, JC Kuo wrote: >> When usb-storage driver detects a UAS capable device, it ignores the >> device if CONFIG_USB_UAS is enabled. usb-storage driver assumes uas >> driver certainly will be loaded. Howeve

Re: [PATCH] usb: storage: skip only when uas driver is loaded

On 7/2/19 12:42 PM, Greg KH wrote: > On Tue, Jul 02, 2019 at 10:36:59AM +0800, JC Kuo wrote: >> On 7/1/19 4:52 PM, Greg KH wrote: >>> On Mon, Jul 01, 2019 at 04:48:48PM +0800, JC Kuo wrote: >>>> When usb-storage driver detects a UAS capable device, it ignores the &g

Re: [PATCH] usb: storage: skip only when uas driver is loaded

On 7/2/19 1:29 PM, JC Kuo wrote: > On 7/2/19 12:42 PM, Greg KH wrote: >> On Tue, Jul 02, 2019 at 10:36:59AM +0800, JC Kuo wrote: >>> On 7/1/19 4:52 PM, Greg KH wrote: >>>> On Mon, Jul 01, 2019 at 04:48:48PM +0800, JC Kuo wrote: >>>>> When usb-storage dr

Re: [PATCH] usb: storage: skip only when uas driver is loaded

On 7/2/19 3:34 PM, Greg KH wrote: > > Footers like this are not allowed on public mailing lists, and forbid me > to respond to... > Hi Greg, I am truly sorry for that. I have just figured out how to tell mail server not to add the footer. Please allow me to query again. Since blacklisting uas k

Re: [PATCH] usb: storage: skip only when uas driver is loaded

On 7/2/19 5:11 PM, Oliver Neukum wrote: > Am Dienstag, den 02.07.2019, 14:56 +0800 schrieb JC Kuo: >> >> Since blacklisting uas kernel module is not a good idea and could break UAS > > Then don't do it. If you don't want a driver loaded for a device > blacklis

Re: [PATCH 2/8] clk: tegra: don't enable PLLE HW sequencer at init

On 7/4/19 8:22 PM, Jon Hunter wrote: > > On 14/06/2019 08:46, JC Kuo wrote: >> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware >> power sequencers' output to enable/disable PLLE. PLLE hardware power >> sequencer has to be enabled only after P

Re: [PATCH 3/8] phy: tegra: xusb: t210: rearrange UPHY init

On 7/4/19 9:32 PM, Jon Hunter wrote: > > On 14/06/2019 08:46, JC Kuo wrote: >> This commit is a preparation for enabling XUSB LP0 support. > > By LP0 do you mean ELPG? If so please stick to using one name for > referring to the power-state in question. > >> It re

[PATCH] xhci: tegra: mbox registers address in"soc" data

Tegra194 XUSB host controller has rearranged mailbox registers. This commit makes mailbox registers address a part of "soc" data so that xhci-tegra driver can be used for Tegra194. Signed-off-by: JC Kuo --- drivers/usb/host/xhci-tegra.c | 51 ++- 1 fi

Re: [PATCH] xhci: tegra: mbox registers address in"soc" data

Thanks for review. I will modify accordingly and submit again. On 9/2/19 3:57 PM, Thierry Reding wrote: > On Mon, Sep 02, 2019 at 11:54:45AM +0800, JC Kuo wrote: >> Tegra194 XUSB host controller has rearranged mailbox registers. This >> commit makes mailbox registers address a par

[PATCH] xhci: tegra: Parameterize mailbox register addresses

Tegra194 XUSB host controller has rearranged mailbox registers. This commit makes mailbox registers address a part of "soc" data so that xhci-tegra driver can be used for Tegra194. Signed-off-by: JC Kuo --- drivers/usb/host/xhci-tegra.c | 58 +-- 1 fi

Re: [PATCH] xhci: tegra: Parameterize mailbox register addresses

On 9/3/19 9:58 PM, Greg KH wrote: > On Mon, Sep 02, 2019 at 04:21:27PM +0800, JC Kuo wrote: >> Tegra194 XUSB host controller has rearranged mailbox registers. This >> commit makes mailbox registers address a part of "soc" data so that >> xhci-tegra driver can be used

Re: [PATCH] xhci: tegra: Parameterize mailbox register addresses

On 9/4/19 1:21 PM, Greg KH wrote: > On Wed, Sep 04, 2019 at 09:43:08AM +0800, JC Kuo wrote: >> On 9/3/19 9:58 PM, Greg KH wrote: >>> On Mon, Sep 02, 2019 at 04:21:27PM +0800, JC Kuo wrote: >>>> Tegra194 XUSB host controller has rearranged mailbox registers. This >&

Re: [PATCH 1/8] clk: tegra: Add PLLE HW power sequencer control

On 7/4/19 8:16 PM, Jon Hunter wrote: > > On 14/06/2019 08:46, JC Kuo wrote: >> PLLE hardware power sequencer has to be enabled after PEX/SATA >> UPHY PLL's sequencers are enabled. >> >> tegra210_plle_hw_sequence_start() for XUSB PADCTL driver to enable >&g