On 19 May 2016 at 01:52, Peter Chen wrote:
>
>
> On Thu, May 19, 2016 at 5:24 AM, Arnd Bergmann wrote:
>>
>> I stumbled over this warning last week, which showed up after I had
>> removed an incorrect patch from my randconfig build setup:
>>
>> drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_
On 18 May 2016 at 16:24, Arnd Bergmann wrote:
> +/*
> + * This abstracts the TCSR register area in Qualcomm SoCs, originally
> + * introduced by Tim Bird as part of the phy-msm-usb.ko device driver,
> + * and split out by Arnd Bergmann into a separate file.
> + *
> + * This file shouldn't reall
a system shutdown would go and access registers and
> uninitialized variables, resulting in below crash.
Works great.
Tested-by: Andy Gross
--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majord...@vger.kernel.org
More majordom
On 19 May 2016 at 05:12, Srinivas Kandagatla
wrote:
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -368,6 +368,15 @@ static void ehci_shutdown(struct usb_hcd *hcd)
> {
> struct ehci_hcd *ehci = hcd_to_ehci(hcd);
>
> + /**
> +* Protect the system from crashing at system shutdown
On 20 May 2016 at 09:31, Alan Stern wrote:
> On Thu, 19 May 2016, Andy Gross wrote:
>
>> On 19 May 2016 at 05:12, Srinivas Kandagatla
>> wrote:
>>
>>
>>
>> > +++ b/drivers/usb/host/ehci-hcd.c
>> > @@ -368,6 +368,15 @@ static void ehci_shu
On 20 May 2016 at 10:57, Alan Stern wrote:
> On Fri, 20 May 2016, Andy Gross wrote:
>
>> On 20 May 2016 at 09:31, Alan Stern wrote:
>> > On Thu, 19 May 2016, Andy Gross wrote:
>> >
>> >> On 19 May 2016 at 05:12, Srinivas Kandagatla
>> >> wr
This patch fixes a suspend/resume issue where the driver is blindly
calling ehci_suspend/resume functions when the ehci hasn't been setup.
This results in a crash during suspend/resume operations.
Signed-off-by: Andy Gross
---
drivers/usb/host/ehci-msm.c | 14 --
1 file change
> instantiated without OTG capability. Instead, relax the dependency
> on having an OTG PHY being present and call usb_add_hcd() directly.
>
> Signed-off-by: Jack Pham
> Signed-off-by: Timur Tabi
Reviewed-by: Andy Gross
--
To unsubscribe from this list: send the line "unsubscribe
On Thu, Dec 10, 2015 at 06:28:55PM -0600, Timur Tabi wrote:
> From: Jack Pham
>
> Allow the EHCI MSM driver to probe against an ACPI enumerated
> device with ID QCOM8040.
>
> Signed-off-by: Jack Pham
> Signed-off-by: Timur Tabi
Reviewed-by: Andy Gross
--
To unsubscribe
n question would revert to
> its default state and must be re-initialized properly.
> Furthermore this may be useful in the future when adding
> PM suspend/resume support.
>
> Signed-off-by: Jack Pham
> Signed-off-by: Timur Tabi
Reviewed-by: Andy Gross
--
To unsubscri
ot continue while kexec boots a new kernel.
>
> Signed-off-by: Azriel Samson
> Signed-off-by: Timur Tabi
Reviewed-by: Andy Gross
--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majord...@vger.kernel.org
More majordomo
From: "Ivan T. Ivanov"
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
drivers/usb/dw
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile|1
ges since v2:
* Several improvements in devicetree bindings description
* Disable regulators in glue layer if there is error during
ioremap.
Changes since first version:
* Split devicetree bindings description file to separate patch
* Address comments for device bindings description
* Fix typo in
From: "Ivan T. Ivanov"
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov
Signed-off
On Fri, Sep 12, 2014 at 12:47:04PM -0500, Felipe Balbi wrote:
> Hi,
>
> On Fri, Sep 12, 2014 at 12:29:45PM -0500, Andy Gross wrote:
> > From: "Ivan T. Ivanov"
> >
> > DWC3 glue layer is hardware layer around Synopsys DesignWare
> > USB3 core. Its pur
On Fri, Sep 12, 2014 at 12:50:23PM -0500, Josh Cartwright wrote:
> Hey Andy-
>
> Mostly cosmetic things below:
>
> On Fri, Sep 12, 2014 at 12:29:46PM -0500, Andy Gross wrote:
> > This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
> > some
&g
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile|1
From: "Ivan T. Ivanov"
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
drivers/usb/dw
From: "Ivan T. Ivanov"
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov
Signed-off
omments for device bindings description
* Fix typo in 'gdsc' requlator name.
Andy Gross (1):
phy: Add Qualcomm DWC3 HS/SS PHY driver
Ivan T. Ivanov (2):
usb: dwc3: qcom: Add device tree binding
usb: dwc3: Add Qualcomm DWC3 glue layer driver
.../devicetree/bindings/phy/qcom-dwc3-u
On Tue, Sep 16, 2014 at 11:27:52AM -0700, Jack Pham wrote:
> Hi Andy,
>
> On Fri, Sep 12, 2014 at 02:28:08PM -0500, Andy Gross wrote:
> > +static int qcom_dwc3_hs_phy_init(struct qcom_dwc3_usb_phy *phy_dwc3)
> > +{
> > + u32 val;
> > +
> > + /*
>
From: "Ivan T. Ivanov"
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
From: "Ivan T. Ivanov"
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov
Signed-off
From: "Ivan T. Ivanov"
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
drivers/usb/dw
These patches add basic support for USB3.0 controllers found
on MSM platforms. USB3.0 core is based on Synopsys DesignWare
SuperSpeed IP.
This work was started by Ivan Ivanov and went through a number of iterations. I
picked these patches up and did a little rework to get them working.
Changes
On Tue, Jul 01, 2014 at 12:04:35AM -0500, Rob Herring wrote:
> > +- clock-names: Should contain the following:
> > + "core" Master/Core clock, have to be >= 125 MHz for SS
> > + operation and >= 60MHz for HS operation
> > +
> > +Optional clocks:
> > +
On Thu, Jul 17, 2014 at 06:30:24AM -0400, kiran.pad...@smartplayin.com wrote:
> Hi,
>
> On Mon, Jun 30, 2014 at 9:33 PM, Andy Gross wrote:
> > From: "Ivan T. Ivanov"
> >
> > These drivers handles control and configuration of the HS
> > and SS USB PH
On Tue, Jun 30, 2015 at 12:56:48PM -0500, Felipe Balbi wrote:
> those two messages are informing that the clock
> doesn't exist; that, however, is a valid situation
> and driver continues just fine by ignoring the error.
Reviewed-by: Andy Gross
--
Qualcomm Innovation Center, Inc
This patch sets the AHBMODE to allow for posted data writes. This
results in higher performance.
Signed-off-by: Andy Gross
---
drivers/usb/chipidea/ci_hdrc_msm.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c
b/drivers/usb/chipidea
This patch sets the AHBMODE to allow for posted data writes. This
results in higher performance.
Signed-off-by: Andy Gross
---
drivers/usb/host/ehci-msm.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index
This patch configures the ChipIdea USB 2.0 controller found on
Qualcomm platforms to post data transfers on the AHB bus. This
yields approximately a 50% increase in performance.
Andy Gross (2):
usb: chipidea: msm: Use posted data writes on AHB
usb: host: ehci-msm: Use posted data writes on
This patch adds documentation for the optional syscon-tcsr property in the
Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to
configure the TCSR USB phy mux register.
Signed-off-by: Andy Gross
---
Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++
1
selection required to get working ports.
Andy Gross (4):
phy: Add Qualcomm DWC3 HS/SS PHY driver
usb: dwc3: qcom: Configure TCSR phy mux register
ARM: dts: qcom: Add DWC3 USB support on IPQ8064
Documentation: usb: dwc3: qcom: Add TCSR mux usage
.../devicetree/bindings/usb/qcom,dwc3.txt
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile| 1
This patch adds Qualcomm DWC3 USB nodes to device tree to enable support for the
DWC3 controller found on IPQ8064/AP148 platforms.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 24 +
arch/arm/boot/dts/qcom-ipq8064.dtsi | 89
This patch adds automatic configuration of the TCSR phy mux register based on
the syscon-tcsr devicetree entry. This configuration is optional, as some
platforms may not require the mux selection.
Signed-off-by: Andy Gross
---
drivers/usb/dwc3/dwc3-qcom.c | 25 +
1 file
On Fri, Nov 20, 2015 at 09:08:46AM -0600, Felipe Balbi wrote:
>
> Hi,
>
> Andy Gross writes:
> > This patch adds documentation for the optional syscon-tcsr property in the
> > Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to
> > configure
On Fri, Nov 20, 2015 at 09:06:33AM -0600, Felipe Balbi wrote:
>
> Hi,
>
> Andy Gross writes:
> > This patch adds automatic configuration of the TCSR phy mux register based
> > on
> > the syscon-tcsr devicetree entry. This configuration is optional, as some
>
On Thu, Jan 22, 2015 at 10:59:14AM -0800, Jack Pham wrote:
> Hi Andy,
>
> On Fri, Sep 12, 2014 at 02:28:08PM -0500, Andy Gross wrote:
> > This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
> > some
> > Qualcomm platforms. This driver uses the gen
On Mon, 7 Jan 2019 at 14:26, Jack Pham wrote:
>
> Hi Jorge,
>
> Sorry for the late reply as I was out during the holiday break.
>
> On Fri, Dec 28, 2018 at 01:38:59PM +0100, Jorge Ramirez wrote:
> > On 12/20/18 18:37, Jack Pham wrote:
> > >Hi Rob, Jorge,
> > >
> > >On Thu, Dec 20, 2018 at 11:05:31
dwc3_qcom_runtime_resume(struct
> device *dev)
> static const struct of_device_id dwc3_qcom_of_match[] = {
> { .compatible = "qcom,dwc3" },
> { .compatible = "qcom,msm8996-dwc3" },
> + { .compatible = "qcom,msm8998-dwc3" },
> { .compatible = "qcom,sdm845-dwc3" },
> { }
Reviewed-by: Andy Gross
42 matches
Mail list logo
