On 19-09-09 14:41:41, jun...@nxp.com wrote:
> From: Li Jun
>
> If ID or VBUS is from external block, don't enable its wakeup
> because it isn't used at all.
>
> Signed-off-by: Li Jun
> ---
> drivers/usb/chipidea/ci_hdrc_imx.c | 8
> drivers/usb/chipidea/ci_hdrc_imx.h | 2 ++
> drive
Hello,
On 9/5/19 8:57 PM, Thinh Nguyen wrote:
Hi,
Roman Kapl wrote:
The address should be set to zero during reset according to the
documentation.
That is for usb reset and not core soft reset, and dwc3 already handles
that case.
I thought that core soft reset is part of the USB reset (it
Am Mittwoch, den 04.09.2019, 19:10 +0200 schrieb Julian Sikorski:
>
>
> Moreover, does this matter that the two Read Capacity errors only appear
> after the device is disconnected?
Hi,
yes it does. However, it didn't in the first log I looked at.
Could you check whether the command the failure
On Tuesday, August 27, 2019 2:16:20 PM CEST, Vicente Bergas wrote:
On Tuesday, August 27, 2019 1:53:04 PM CEST, Felipe Balbi wrote:
Hi,
Vicente Bergas writes:
On Saturday, August 17, 2019 7:41:40 PM CEST, Vicente Bergas wrote:
Otherwise the device keeps writing to memory after kexec and dist
W dniu 09.09.2019 o 14:45, Oliver Neukum pisze:
Am Mittwoch, den 04.09.2019, 19:10 +0200 schrieb Julian Sikorski:
Moreover, does this matter that the two Read Capacity errors only appear
after the device is disconnected?
Hi,
yes it does. However, it didn't in the first log I looked at.
Coul
Hi,
Roman Kapl wrote:
> Hello,
>
> On 9/5/19 8:57 PM, Thinh Nguyen wrote:
>> Hi,
>>
>> Roman Kapl wrote:
>>> The address should be set to zero during reset according to the
>>> documentation.
>>
>> That is for usb reset and not core soft reset, and dwc3 already handles
>> that case.
>
> I thought
Change the macro name DWC3_GTXFIFOSIZ_TXFDEF to DWC3_GTXFIFOSIZ_TXFDEP
to match with the register name GTXFIFOSIZ.TXFDEP.
Signed-off-by: Thinh Nguyen
---
drivers/usb/dwc3/core.h | 4 ++--
drivers/usb/dwc3/gadget.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers
Currently the calculation of max packet size limit for IN endpoints is
too restrictive. This prevents a matching of a capable hardware endpoint
during configuration. Below is the minimum recommended HW configuration
to support a particular endpoint setup from the databook:
For OUT endpoints, the d
