On Wed, Aug 28, 2019 at 4:43 PM Rafael J. Wysocki wrote:
> With the git branch mentioned previously merged in, you can enable
> dynamic debug in device_pm.c, repeat the PM-runtime test and collect
> the log. There should be some additional messages from the ACPI layer
> in it.
That's useful, tha
Hi,
> static int intel_xhci_usb_set_role(struct device *dev, enum usb_role role)
> @@ -44,7 +52,7 @@ static int intel_xhci_usb_set_role(struct device *dev, enum
> usb_role role)
> struct intel_xhci_usb_data *data = dev_get_drvdata(dev);
> unsigned long timeout;
> acpi_status st
On 8/28/19 9:57 AM, Mathias Nyman wrote:
I'll submit a proper patch
-Mathias
Thanx very much
Harri
In platforms like Cherrytrail, 'SW switch enable' bit
should not be enabled for role switch. This patch
adds a property to Intel USB Role Switch platform driver
to denote that SW switch should be disabled in
Cherrytrail devices.
Signed-off-by: Saranya Gopal
Signed-off-by: Balaji Manoharan
Sugges
Enable static DRD mode in Intel platforms which guarantees
successful role switch all the time. This fixes issues like
software role switch failure after cold boot and issue with
role switch when USB 3.0 cable is used. But, do not enable
static DRD mode for Cherrytrail devices which rely on firmwar
On Thu, Aug 29, 2019 at 04:12:06PM +0530, Saranya Gopal wrote:
> In platforms like Cherrytrail, 'SW switch enable' bit
> should not be enabled for role switch. This patch
> adds a property to Intel USB Role Switch platform driver
> to denote that SW switch should be disabled in
> Cherrytrail device
On Thu, Aug 29, 2019 at 04:12:07PM +0530, Saranya Gopal wrote:
> Enable static DRD mode in Intel platforms which guarantees
> successful role switch all the time. This fixes issues like
> software role switch failure after cold boot and issue with
> role switch when USB 3.0 cable is used. But, do n
Hi Saranya,
On 29-08-19 12:42, Saranya Gopal wrote:
Enable static DRD mode in Intel platforms which guarantees
successful role switch all the time. This fixes issues like
software role switch failure after cold boot and issue with
role switch when USB 3.0 cable is used. But, do not enable
static
> -Original Message-
> From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
> ow...@vger.kernel.org] On Behalf Of Hans de Goede
> Sent: Thursday, August 29, 2019 4:34 PM
> To: Gopal, Saranya ;
> heikki.kroge...@linux.intel.com
> Cc: gre...@linuxfoundation.org; Nyman, Mathias
> ; linux
In platforms like Cherrytrail, 'SW switch enable' bit
should not be enabled for role switch. This patch
adds a property to Intel USB Role Switch platform driver
to denote that SW switch should be disabled in
Cherrytrail devices.
Signed-off-by: Saranya Gopal
Signed-off-by: Balaji Manoharan
Sugges
Enable static DRD mode in Intel platforms which guarantees
successful role switch all the time. This fixes issues like
software role switch failure after cold boot and issue with
role switch when USB 3.0 cable is used. But, do not enable
static DRD mode for Cherrytrail devices which rely on firmwar
* Tony Lindgren [190828 08:11]:
> With commit 594632efbb9a ("usb: musb: Adding musb support for OMAP4430")
> Looks like always calling otg_set_vbus() causes flakeyness enumerating when
> droid4 is connected to a lapdock. In this case lapdock runs in USB carkit
> type mode and feeds the VBUS.
I do
Questions like this should always be CC'ed to the appropriate mailing
list. (And note that the mailing list does not accept messages in HTML
format.)
On Thu, 29 Aug 2019, sandeep krishnaswamy wrote:
> Hi Alan,
>
>
>
> We are using the Android 8.x (i.e Android ‘O’) with Android kernel 4.9.18
The system can hit a deadlock if xhci adapter breaks while initializing.
The deadlock is between two threads: thread 1 is tearing down the
adapter and is stuck in usb_unlocked_disable_lpm waiting to lock the
hcd->handwidth_mutex. Thread 2 is holding this mutex (while still trying
to add a usb d
W dniu 24.08.2019 o 09:08, Julian Sikorski pisze:
W dniu 23.08.2019 o 23:23, Oliver Neukum pisze:
Am Freitag, den 23.08.2019, 16:21 +0200 schrieb Julian Sikorski:
I did some further digging regarding whether this is a regression: the
quirk file on the laptop is from 15 July 2014. The machine i
From: Ajay Gupta
CCGx controller used on NVIDIA GPU card has two separate display
altmode for two DP pin assignments. UCSI specification doesn't
prohibits using separate display altmode.
Current UCSI Type-C framework expects only one display altmode for
all DP pin assignment. This patch squashes
While testing our host system using Microsoft's usb stack against our
gadget for various BESL values, we found an issue with their usb stack
when the recommended baseline BESL value is 0 (125us) or when the deep
BESL is 1 or less. The Windows host will issue a usb reset immediately
after it receive
The errata description is:
Workaround for Default Duration of LFPS Handshake Signaling for
Device-Initiated U1 Exit is too short.
The default duration of the LFPS handshake generated by USB3380 for a
device-initiated U1-exit may not be
long enough for certain SuperSpeed downstream ports (SuperSp
The split into multiple structures of the "ll" register bank is
impractical. It makes it hard to add ll_lfps_timers_2 which is
at offset 0x794, which is outside of the existing "lfps" structure
and would require us to add yet another one.
Instead, move all the "ll" registers into a single usb338x_
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