On Thu, Nov 15, 2018 at 03:16:04PM +0100, Nikolaj Fogh wrote:
> On 11/15/18 9:24 AM, Johan Hovold wrote:
> > On Tue, Nov 13, 2018 at 08:19:44PM +0100, Nikolaj Fogh wrote:
> >> On 11/12/18 10:54 AM, Johan Hovold wrote:
> >>> On Wed, Oct 31, 2018 at 09:16:48PM +0100, Nikolaj Fogh wrote:
> I have
On Thu, 2018-11-15 at 09:56 -0500, Alan Stern wrote:
> On Thu, 15 Nov 2018, Oliver Neukum wrote:
>
> >
> > On Do, 2018-11-15 at 12:45 +, Mayuresh Kulkarni wrote:
> > >
> > >
> > > Understood this for remote-wake part.
> > >
> > > But still unclear about step (1) for host-wake as below (ple
On Fri, 16 Nov 2018, Mayuresh Kulkarni wrote:
> Thanks for the comments. Based on the info so far, attempting to summarize the
> probable solution, to ensure that I understand it clearly -
>
> Facts -
> 1. USBFS driver grabs a PM ref-count in .open and drops it in .close which
> means
> USB devi
Improve baud-rate generation by using rounding-to-closest instead of
truncation in divisor calculation.
Results have been verified by logic analyzer on an FT232RT (232BM) chip.
The following table shows the wanted baud rate, the baud rate obtained
with the old method (truncation), with the new me
Hi Felipe,
On 6/28/2018 11:24 PM, Felipe Balbi wrote:
> (no top-posting!!)
>
> liangshengjun writes:
>
>> Hi balbi,
>>
>> It means that the mainline keep checking stall status first before
>> handle clear-halt request? as usb spec, it's actually okay to send
>> Clear Halt at any time. But dwc3 c
From: Sandeep Singh
Occasionally AMD SNPS 3.0 xHC does not respond to
CSS when set, also it does not flag anything on SRE and HCE
to point the internal xHC errors on USBSTS register. This stalls
the entire system wide suspend and there is no point in stalling
just because of xHC CSS is not respon
Hi Sandeep,
> On Nov 16, 2018, at 16:21, Singh, Sandeep wrote:
>
> From: Sandeep Singh
>
> Occasionally AMD SNPS 3.0 xHC does not respond to
> CSS when set, also it does not flag anything on SRE and HCE
> to point the internal xHC errors on USBSTS register. This stalls
> the entire system wide
Hi Andrew, Florian,
>>>
>>> So the point is that MAC firmware is managing SERDES and system interface
>>> link.
>>
>> Linux can manage that SERDES link between the MAC and the PHY. There
>> are two ways this can go:
>>
>> 1) You use phylib. When the PHY reports link, the adjust_link callback
>>
On Fri, Nov 16, 2018 at 02:36:56PM +0800, JackyChou wrote:
> From: JackyChou
>
> Add a new PID 0x7843 to the driver.
> Let the new products be able to set up 3 serial ports with the driver.
>
> Because the development of new product is based on 4 serial ports,
> but some users only need 3 seria
On 15/11/18 18:06, woojung@microchip.com wrote:
Hi Ben,
-Original Message-
From: netdev-ow...@vger.kernel.org On Behalf Of
Ben Dooks
Sent: Wednesday, November 14, 2018 6:50 AM
To: net...@vger.kernel.org
Cc: oneu...@suse.com; da...@davemloft.net; linux-usb@vger.kernel.org; linux-
k
Hi Alan,
thanks for the review.
On Thu, 2018-11-15 at 14:24 -0500, Alan Stern wrote:
> On Thu, 15 Nov 2018, Nicolas Saenz Julienne wrote:
>
> > An URB submission error in the HUB's endpoint completion function
> > renders the whole HUB device unresponsive. This patch introduces a
> > routine that
On 14/11/18 18:47, Alan Stern wrote:
On Wed, 14 Nov 2018, Ben Dooks wrote:
From: Ben Dooks
At least some systems benefit with less scheduling if the NAK count
value is set higher than the default 4. For instance a Tegra3 with
an SMSC9512 showed less interrupt load when this was changed to 14.
On Fri, 16 Nov 2018, Ben Dooks wrote:
> On 14/11/18 18:47, Alan Stern wrote:
> > On Wed, 14 Nov 2018, Ben Dooks wrote:
> >
> >> From: Ben Dooks
> >>
> >> At least some systems benefit with less scheduling if the NAK count
> >> value is set higher than the default 4. For instance a Tegra3 with
>
The tasklet initialisation would be better done by tasklet_init()
instead of assuming all the fields are in an ok state by default.
Note, this does not fix any known bug.
Signed-off-by: Ben Dooks
---
drivers/net/usb/usbnet.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/
On Fri, 16 Nov 2018, Nicolas Saenz Julienne wrote:
> Hi Alan,
> thanks for the review.
>
> On Thu, 2018-11-15 at 14:24 -0500, Alan Stern wrote:
> > On Thu, 15 Nov 2018, Nicolas Saenz Julienne wrote:
> >
> > > An URB submission error in the HUB's endpoint completion function
> > > renders the who
Hi,
On 15.11.2018 10:09, Felipe Balbi wrote:
>
> Hi,
>
> Todor Tomov writes:
>
>> Hello,
>>
>> After I apply this patch on 4.14 (or receive it with 4.14.70) I see a
>> regression with
>> the Qualcomm QUSB2 phy driver. I'm testing on a Dragonboard 820c.
>> In boot log I get:
>>
>> [4.52550
> Production dongles will always have firmware fully controlling all the phy.
> Thus, I think in next series we'll just cut off all the direct phy
> access code.
O.K, but that is also a shame. The PHY i have has all sorts of nice
things, MACSEC, temperature sensors, PTP, cable tests logic,
etc. Wi
The BTUSB_INTEL and BTUSB_INTEL_NEW have common functions & quirks are
assigned to hdev structure. Lets collect them together instead of
repeating them in different code branches.
Signed-off-by: Rajat Jain
---
drivers/bluetooth/btusb.c | 27 ---
1 file changed, 12 inserti
From: Dmitry Torokhov
USB devices permanently connected to USB ports may be described in ACPI
tables and share ACPI devices with ports they are connected to. See [1]
for details.
This will allow us to describe sideband resources for devices, such as,
for example, hard reset line for BT USB contr
If the platform provides it, use the reset gpio to reset the BT
chip (requested by the HCI core if needed). This has been found helpful
on some of Intel bluetooth controllers where the firmware gets stuck and
the only way out is a hard reset pin provided by the platform.
Signed-off-by: Rajat Jain
From: Dmitry Torokhov
In preparation for handling embedded USB devices let's split
usb_acpi_find_companion() into usb_acpi_find_companion_for_device() and
usb_acpi_find_companion_for_port().
Signed-off-by: Dmitry Torokhov
Signed-off-by: Rajat Jain
---
drivers/usb/core/usb-acpi.c | 133 +++
There can be error conditions within Intel BT firmware that can cause it
to get stuck, with the only way out being toggle the reset pin to the
device. (I do not have the details about the issues that lead to such
conditions, Intel folks copied here can elaborate if needed). Thus, this
is an effor t
Add a quirk and a hook to allow the HCI core to reset the BT chip
if needed (after a number of timed out commands). Use that new hook to
initiate BT chip reset if the controller fails to respond to certain
number of commands (currently 5) including the HCI reset commands.
This is done based on a ne
Hi,
On 2018/11/13 0:02, Rob Herring wrote:
> On Sat, Oct 27, 2018 at 05:58:11PM +0800, Yu Chen wrote:
>> This patch adds binding descriptions to support the dwc3 controller
>> on HiSilicon SoCs and boards like the HiKey960.
>>
>> Cc: Greg Kroah-Hartman
>> Cc: Rob Herring
>> Cc: Mark Rutland
>>
From: Ben Dooks
Date: Wed, 14 Nov 2018 11:50:18 +
> This is a series of a few driver cleanups and some fixups of the code
> for the SMSC95XX driver. There have been a few reviews, and the issues
> have been fixed so this should be ready for merging.
>
> I will work on the tx-alignment and th
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