Andy Shevchenko writes:
> On Thu, Jul 26, 2018 at 5:01 PM, Gevorg Sahakyan
> wrote:
>> Declared dwc2_check_core_endianness() function for dynamicly check
>> core endianness.
>> Added needs_byte_swap flag to hsotg structure, and depending on
>> flag swap value inside dwc2_readl/writel functions.
Hi,
On 7/26/2018 7:27 PM, Andy Shevchenko wrote:
> On Thu, Jul 26, 2018 at 5:00 PM, Gevorg Sahakyan
> wrote:
>> dwc2_readl_rep/dwc2_writel_rep functions using readl/writel in a
>> loop.
> Why this is better? Any regression or what?
>
dwc2_readl_rep/dwc2_writel_rep used instead of
ioread32_rep/iowr
Declared dwc2_check_core_endianness() function for dynamicly check
core endianness.
Added needs_byte_swap flag to hsotg structure, and depending on
flag swap value inside dwc2_readl/writel functions.
Signed-off-by: Gevorg Sahakyan
---
drivers/usb/dwc2/core.h | 15 +--
drivers/us
Hi,
Benjamin Herrenschmidt writes:
> On Fri, 2018-07-27 at 09:53 +0300, Felipe Balbi wrote:
>> Benjamin Herrenschmidt writes:
>>
>> > On Fri, 2018-07-27 at 08:38 +1000, Benjamin Herrenschmidt wrote:
>> > > On Thu, 2018-07-26 at 14:01 +0300, Felipe Balbi wrote:
>> > > > Hi,
>> > > >
>> > > > B
Hi,
Gevorg Sahakyan writes:
> @@ -1164,12 +1166,21 @@ struct dwc2_hsotg {
> /* Normal architectures just use readl/write */
> static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
> {
> - return readl(hsotg->regs + offset);
> + u32 val;
> +
> + val = readl(hsotg
Declared dwc2_check_core_endianness() function for dynamicly check
core endianness.
Added needs_byte_swap flag to hsotg structure, and depending on
flag swap value inside dwc2_readl/writel functions.
Signed-off-by: Gevorg Sahakyan
---
drivers/usb/dwc2/core.h | 15 +--
drivers/usb
Hi Felipe,
On 7/27/2018 12:26, Gevorg Sahakyan wrote:
> Declared dwc2_check_core_endianness() function for dynamicly check
> core endianness.
> Added needs_byte_swap flag to hsotg structure, and depending on
> flag swap value inside dwc2_readl/writel functions.
>
> Signed-off-by: Gevorg Sahakyan
hi,
Grigor Tovmasyan writes:
>> @@ -395,6 +412,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
>> dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
>> (unsigned long)res->start, hsotg->regs);
>>
>> +hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg)
On Fri, Jul 27, 2018 at 2:02 AM, Thinh Nguyen wrote:
> On 7/26/2018 2:59 PM, Thinh Nguyen wrote:
>> On 7/26/2018 2:32 PM, Andy Shevchenko wrote:
>>> On Thu, Jul 26, 2018 at 11:52 PM, Thinh Nguyen
>>> wrote:
dwc_usb31 does not support OTG mode. If the controller supports DRD but
the dr_m
On Fri, Jul 27, 2018 at 1:14 PM, Felipe Balbi wrote:
>> +
>> + /*
>> +* dwc_usb31 does not support OTG mode. If the controller
>> +* supports DRD but the dr_mode is not specified or set
>> to OTG,
>> +* then se
Hi,
Andy Shevchenko writes:
> On Fri, Jul 27, 2018 at 2:02 AM, Thinh Nguyen
> wrote:
>> On 7/26/2018 2:59 PM, Thinh Nguyen wrote:
>>> On 7/26/2018 2:32 PM, Andy Shevchenko wrote:
On Thu, Jul 26, 2018 at 11:52 PM, Thinh Nguyen
wrote:
> dwc_usb31 does not support OTG mode. If the
To start ISOC transfers in handlers dwc2_gadget_handle_nak() and
dwc2_gadget_handle_out_token_ep_disabled() driver reads current frame
number, based on which, set target frame number to start first ISOC
transfer.
In case if system's high IRQ latency and multiple EP's asserted
interrupt in same fra
Greetings,
I have a custom design with a Fairchild FUSB302 Type-C chip driver
that I'm testing with Linux 4.17 and a BTI AC-60TC 60W charger. For
this design we are using Type-C as a power/charger input only - no
USB2/3 is connected. The board consumes approximately 12W typical
which doesn't leave
Hi Felipe,
On Thu, Jul 26, 2018 at 01:51:35PM +0300, Felipe Balbi wrote:
> Eugeniu Rosca writes:
>
> > From: Andreas Pape
> >
> > Via p_chmask/c_chmask the user can define whether uac2 shall support
> > playback and/or capture. This has only effect on the created ALSA device,
> > but not on the
DWC3 must check for the BUFSIZ and update the req->remaining
regardless of transfer alignment. Returning early from transfer OUT
unalignment will skip updating the req->remaining.
Fixes: c6267a51639b ("usb: dwc3: gadget: align transfers to wMaxPacketSize")
Signed-off-by: Thinh Nguyen
---
drivers
For OUT transfers, the total size (total TRB buffer allocation) must be
a multiple of MaxPacketSize even if software is expecting a fixed
non-multiple of MaxPacketSize transfer from the host.
(DWC_usb31 programming guide section 4.2.5)
So, to calculate the actual bytes written (OUT transfer), do:
endpoint->maxpacket is not updated after setting the
usb_set_maxpacket_limit() on endpoint enable. The MaxPacketSize can be
different than the endpoint->maxpacket_limit.
DWC3 has been consistently using MaxPacketSize from the endpoint's
descriptor, so let's keep it consistent and use the MaxPacket
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