Am Mittwoch, den 27.09.2017, 14:14 +0800 schrieb Daniel Drake:
> There are no errors in the logs showing any suspend/resume-related issues.
> When the system wakes up due to the modem, log-wise it appears to be a
> normal resume.
>
> Does anyone have any suggestions for how we can investigate furt
Am Dienstag, den 26.09.2017, 08:19 -0700 schrieb Doug Anderson:
>
> I know that for at least some of the adapters in the CDC Ethernet
> blacklist it was claimed that the CDC Ethernet support in the adapter
> was kinda broken anyway so the blacklist made sense. ...but for the
> Linksys Gigabit ada
Hi,
Alan Stern writes:
> On Tue, 26 Sep 2017, Felipe Balbi wrote:
>
>> > Does uvc use isochronous transfers? I assume it would, since it's a
>> > video protocol.
>>
>> yes, it does :-)
>>
>> > dummy-hcd does not support isochronous. I don't know what would happen
>>
>> really? Then why is
On 26.09.2017 22:08, Adrian Bocaniciu wrote:
On Tue, 26 Sep 2017 09:53:23 +0300
Mathias Nyman wrote:
Do you have any more details, logs or documentation about these 10Gbps ASM1142
bugs in xHCI driver?
I'd be interested in getting that fixed
Thanks
Mathias
I know exactly what must be chang
This patch fixes two issues:
- the usbhsf_fifo_clear() is possible to cause 10 msec delay if
the pipe is RX direction and empty because the FRDY bit will never
be set to 1 in such case.
- sets the BCLR of {C,Dn}FIFOCTR to 1 even when it's non-DCP pipe and
the FRDY bit sets to 0.
Fixes:
The atmel serial port driver reported the following warning on suspend:
atmel_usart f802.serial: ttyS1: Unable to drain transmitter
As the ATMEL_US_TXEMPTY status bit in ATMEL_US_CSR is always cleared
when the transmitter is disabled, we need to know the transmitter's
state to return the real
On Wed, Sep 27, 2017 at 05:04:05PM +0900, Yoshihiro Shimoda wrote:
> This patch fixes two issues:
> - the usbhsf_fifo_clear() is possible to cause 10 msec delay if
>the pipe is RX direction and empty because the FRDY bit will never
>be set to 1 in such case.
> - sets the BCLR of {C,Dn}FIF
The controller used by a flexcom module is configured at boot, and left
alone after this. As the configuration will be lost after backup mode,
restore the state of the flexcom driver on resume.
Signed-off-by: Romain Izard
Acked-by: Nicolas Ferre
Tested-by: Nicolas Ferre
---
drivers/mfd/atmel-f
Save and restore registers for the PWM on suspend and resume, which
makes hibernation and backup modes possible.
Signed-off-by: Romain Izard
Acked-by: Nicolas Ferre
---
drivers/pwm/pwm-atmel-tcb.c | 63 +++--
1 file changed, 61 insertions(+), 2 deletions(
Wait for the syncronization of all clocks when resuming, not only the
UPLL clock. Do not use regmap_read_poll_timeout, as it will call BUG()
when interrupts are masked, which is the case in here.
Signed-off-by: Romain Izard
Acked-by: Ludovic Desroches
Acked-by: Nicolas Ferre
---
drivers/clk/at
During backup mode, the contents of all registers will be cleared as the
SoC will be completely powered down. For a product that boots on NAND
Flash memory, the bootloader will obviously use the related controller
to read the Flash and correct any detected error in the memory, before
handling back
When an Atmel SoC is suspended with the backup mode, the USB bus will be
powered down. As this is expected, do not return an error to the driver
core when ehci_resume detects it.
Signed-off-by: Romain Izard
Acked-by: Nicolas Ferre
---
drivers/usb/host/ehci-atmel.c | 3 ++-
1 file changed, 2 ins
While the core of the backup mode for SAMA5D2 has been integrated in
v4.13, it is far from complete. Individual controllers in the chip have
drivers that do not support the reset of the registers during suspend,
and they need to be adapted to handle it.
The first patch uses the clock wakeup code f
Hi Greg,
> -Original Message-
> From: Greg KH
> Sent: Wednesday, September 27, 2017 5:37 PM
>
> On Wed, Sep 27, 2017 at 05:04:05PM +0900, Yoshihiro Shimoda wrote:
> > This patch fixes two issues:
> > - the usbhsf_fifo_clear() is possible to cause 10 msec delay if
> >the pipe is RX di
The contents of the System Clock Status Register (SCSR) needs to be
restored into the System Clock Enable Register (SCER).
As the bootloader will restore some clocks by itself, the issue can be
missed as only the USB controller, the LCD controller, the Image Sensor
controller and the programmable
From: Romain Izard
When an AT91 programmable clock is declared in the device tree, register
it into the Power Management Controller driver. On entering suspend mode,
the driver saves and restores the Programmable Clock registers to support
the backup mode for these clocks.
Signed-off-by: Romain
QUSB-v2 and QMP-v3 USB PHYs are present on Qualcomm's 14nm
and 10nm SOCs.
This patch series adds support for runtime PM for these
USB PHYs and adds fixes in drivers to follow PHY reset and
initialization sequence as per hardware programming manual.
Changes since v1:
- Incorporated review comments.
lane0_power_present signal must be asserted of hardware to
operate properly in SS device mode. On some platforms where VBUS
line is not connected to SS QMP PHY there is SS_PHY_CTRL register
in QSCRATCH wrapper that can be used by software to override VBUS.
Signed-off-by: Manu Gautam
---
drivers/
Disable clocks as part of PHY suspend. This also requires enabling
PHY autonomous mode to detect lfps/rx_det in suspend state.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 182 +++-
drivers/phy/qualcomm/phy-qcom-qmp.h | 3 +
2 files chang
Disable clocks and dp/dm asynchronous interrupts from
PHY as part of runtime suspend.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 159 ++
1 file changed, 159 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/ph
QMP V3 USB3 PHY is a DP USB combo PHY with
dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related
to type-c or DP. Add support for dp_com region
and secondary rx/tx lanes initialization.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c |
VBUS signal coming from PHY must be asserted in device for
controller to start operation or assert pull-up. For some
platforms where VBUS line is not connected to PHY there is
HS_PHY_CTRL register in QSCRATCH wrapper that can be used
by software to override VBUS signal going to controller.
Signed-
Update compatible string and clock names for QMP version V3
USB PHY.
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
b/Documentat
New revision (v3) of QMP PHY uses different offsets
for almost all of the registers. Hence, move these
definitions to header file so that updated offsets
can be added for QMP v3.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 119 +--
drivers/phy
Registers offsets for QMP V3 PHY are changed from
previous versions (1/2), update same in header file.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 149
1 file changed, 149 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 131 --
1 file changed, 95 insertions(+),
Use register layout to add additional registers present
on QUSB2 PHY V2 version for PHY initialization.
Other than new registers on V2, following two register's
offset and bit definitions are different: POWERDOWN control
and PLL_STATUS.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qco
PHY block or asynchronous reset requires signal
to be asserted before de-asserting. Driver is only
de-asserting signal which is already low, hence
reset operation is a no-op. Fix this by asserting
signal first. Also, resetting requires PHY clocks
to be turned ON only after reset is finished. Fix
th
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff -
Update generic compatible string for QUSB2 V2 PHY. This will allow
all targets using QUSB2 V2 use same string.
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/
PHY must be powered on before turning ON clocks and
attempting to initialize it. Driver is exposing
separate init and power_on routines for this.
Apparently USB dwc3 core driver performs power-on
after init. Also, poweron and init for QUSB2 PHY
need to be executed together always, hence remove
powe
From: Vivek Gautam
Move from using array of clocks to clk_bulk_* APIs that
are available now.
Signed-off-by: Vivek Gautam
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 -
1 file changed, 16 insertions(+), 34 deletions(-)
diff --gi
From: Vivek Gautam
Pipe clock comes out of the phy and is available as long as
the phy is turned on. Clock controller fails to gate this
clock after the phy is turned off and generates a warning.
/ # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on'
[ 33.048585] [ cut here
PHY must be powered on before turning ON clocks and
attempting to initialize it. Driver is exposing
separate init and power_on routines for this.
Apparently USB dwc3 core driver performs power-on after
init. Also, poweron and init for QMP PHY need to be
executed together always, hence remove powero
This is useful to find out the root cause when the Super Speed doesn't
work. Such as when the T-PHY is switched to PCIe or SATA, and affects
Super Speed function, the check will fail.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c |4
1 file changed, 4 insertions(+)
diff -
There are mcu_bus and dma_bus clocks needed to be controlled by
driver on some SoCs, so add them as optional ones
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c | 79 ---
drivers/usb/host/xhci-mtk.h |2 ++
2 files changed, 62 insertions(
Add a new optional property to disable u3ports
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/usb/mediatek,mtk-xhci.txt |2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
b/Documentation/devicetree/bindings/usb/mediatek
Remove dummy clocks for usb wakeup and add optional ones for
MCU_BUS_CK and DMA_BUS_CK.
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/usb/mediatek,mtk-xhci.txt | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/u
Due to all MediaTek SoCs with xHCI host controller use this
driver, remove limitation for specific SoCs
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/Kconfig |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index fa
The wakeup debounce clocks for each ports in fact are not
needed, so remove them.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c | 33 -
drivers/usb/host/xhci-mtk.h |2 --
2 files changed, 35 deletions(-)
diff --git a/drivers/usb/host/xhci-mtk.
This patch uses the simpler dma_set_mask_and_coherent() instead of
doing these as separate steps
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c |7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
inde
Make use of ports count from xhci but not from ippc in
xhci_mtk_sch_init()
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk-sch.c |3 ++-
drivers/usb/host/xhci-mtk.c |3 ---
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/host/xhci-mtk-sch.c b/driv
Add support to disable specific usb3 ports, it's useful when
usb3 phy is shared with PCIe or SATA, because we should disable
the corresponding usb3 port if the phy is used by PCIe or SATA.
Sometimes it's helpful to analyse and solve problems.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci
This patch set is based on the Felipe's usb.git / testing/fixes branch
(The commit is 7661ca09b2ff98f48693f431bb01fed62830e433).
Changes from v1:
- Devides two fix things in a patch to two patches.
Yoshihiro Shimoda (2):
usb: renesas_usbhs: fix the BCLR setting condition for non-DCP pipe
u
This patch fixes an issue that the usbhsf_fifo_clear() is possible
to cause 10 msec delay if the pipe is RX direction and empty because
the FRDY bit will never be set to 1 in such case.
Fixes: e8d548d54968 ("usb: renesas_usbhs: fifo became independent from pipe.")
Cc: # v3.1+
Signed-off-by: Yoshi
This patch fixes an issue that the driver sets the BCLR bit of
{C,Dn}FIFOCTR register to 1 even when it's non-DCP pipe and
the FRDY bit of {C,Dn}FIFOCTR register is set to 1.
Fixes: e8d548d54968 ("usb: renesas_usbhs: fifo became independent from pipe.")
Cc: # v3.1+
Signed-off-by: Yoshihiro Shimod
The sunxi musb has a bug where sometimes it will generate a babble
error on device disconnect instead of a disconnect IRQ. When this
happens the musb controller switches from host mode to device mode
(it clears MUSB_DEVCTL_HM/MUSB_DEVCTL_SESSION and sets
MUSB_DEVCTL_BDEVICE) and gets stuck in this
Hi Oliver thank you for your reply.
Apologies for now replying from gmail. I'm being told my crjb.net
address is failing SPF and that I have to shoehorn this email into
plain-text for you. Here we go :)
I must correct/clarify that the browser forward and back buttons seem to
work in chrome a
When dr_mode is set as USB_DR_MODE_HOST, it's better to try to
get optional vbus, this can increase flexibility, although we
can set vbus as always on for regulator or put it in host driver
to turn it on.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3_plat.c |8
1 file change
Treat dr_mode of USB_DR_MODE_UNKNOWN as USB_DR_MODE_OTG to
enhance functional robustness.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3_plat.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
index 7c
add support for 36-bit DMA address
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3.h | 17 ++-
drivers/usb/mtu3/mtu3_core.c| 34 -
drivers/usb/mtu3/mtu3_hw_regs.h | 10
drivers/usb/mtu3/mtu3_qmu.c | 102 ---
4
There are mcu_bus and dma_bus clocks needed to be turned on/off by
driver on some SoCs, so add them as optional ones
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3.h |5 ++
drivers/usb/mtu3/mtu3_plat.c | 121 --
2 files changed, 86 inserti
When fail to get irq number, platform_get_irq() may return
-EPROBE_DEFER, but we ignore it and always return -ENODEV,
so fix it.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3_core.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3_core.c b/
In order to keep manual DRD switch independent on IDDIG interrupt,
make use of FORCE/RG_IDDIG instead of IDDIG EINT interrupt to
implement manual DRD switch function.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3.h | 18
drivers/usb/mtu3/mtu3_dr.c | 61 +
Support SuperSpeedPlus for usb3.1 device IP
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3.h|1 +
drivers/usb/mtu3/mtu3_core.c | 14 +++---
drivers/usb/mtu3/mtu3_gadget.c |3 ++-
drivers/usb/mtu3/mtu3_gadget_ep0.c | 16
drivers/us
The wakeup debounce clocks for each ports in fact are not
needed, so remove them.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3.h |4 ---
drivers/usb/mtu3/mtu3_host.c | 57 +++---
2 files changed, 4 insertions(+), 57 deletions(-)
diff --git
Add support to disable specific usb3 ports, it's useful when
usb3 phy is shared with PCIe or SATA, because we should disable
the corresponding usb3 port if the phy is used by PCIe or SATA.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3.h |3 +++
drivers/usb/mtu3/mtu3_host.c | 1
Driver currently notifies only USB2 PHY on USB mode change.
Extend this to USB3 PHY so that PHY drivers based on the
mode can release system resources - clocks, regulators etc.
Additionally Qualcomm QMP and QUSB2 PHY drivers need to
override VBUS signal in PHY wrapper in device mode as USB
VBUS lin
Driver powers-off PHYs and reinitializes DWC3 core and gadget on
resume. While this works fine for gadget mode but in host
mode there is not re-initialization of host stack. Also, resetting
bus as part of bus_suspend/resume is not correct which could affect
(or disconnect) connected devices.
Fix th
Driver currently resumes and increments pm usage_count
of its child device (dwc3 main) from its runtime_resume
handler. This requires dwc3 runtime_resume to perform
pm_runtime_put to decrement the pm usage_count. However
runtime_put from dwc3 happens for non pci drivers
(e.g. dwc3-if-simple.c) as w
We are not releasing 'buf' memory on failure or disconnect a device.
Adding 'u8 *buf' as part of 'lan78xx_net' structure to make proper
handle for 'buf'.
Now releasing 'buf' memory on failure. It's allocate first in
lan78xx_probe() and it should be freed last in lan78xx_disconnect().
Signed-off-b
On Wed, Sep 27, 2017 at 1:18 PM, Arvind Yadav wrote:
> We are not releasing 'buf' memory on failure or disconnect a device.
>
> Adding 'u8 *buf' as part of 'lan78xx_net' structure to make proper
> handle for 'buf'.
> Now releasing 'buf' memory on failure. It's allocate first in
> lan78xx_probe() a
On Wed, Sep 27, 2017 at 2:06 PM, Andrey Konovalov wrote:
> On Wed, Sep 27, 2017 at 1:18 PM, Arvind Yadav
> wrote:
>> We are not releasing 'buf' memory on failure or disconnect a device.
>>
>> Adding 'u8 *buf' as part of 'lan78xx_net' structure to make proper
>> handle for 'buf'.
>> Now releasing
apologies, trying to sort out the SPF errors I've been getting
On 25/09/17 22:22, Oliver Neukum wrote:
Am Sonntag, den 24.09.2017, 13:14 +1000 schrieb Christian Bullow:
Upon depressing the DIP switch or forward/backward buttons, the mouse
freezes and is unresponsive. The only way to fix this i
On Wed, 27 Sep 2017, Michel Hermier wrote:
> Le 27 sept. 2017 07:42, "Alan Stern" a écrit :
> > - for (n = 0; n < hdesc->bNumDescriptors; n++)
> > + num_descriptors = min_t(int, hdesc->bNumDescriptors,
> > + (hdesc->bLength - 6) / 3);
> > + for (n
Hi Li,
[auto build test ERROR on staging/staging-testing]
[also build test ERROR on v4.14-rc2 next-20170927]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Li-Jun/staging-typec-tcpci-move-out
Hi!
I've got the following report while fuzzing the kernel with syzkaller.
On commit e19b205be43d11bff638cad4487008c48d21c103 (4.14-rc2).
gadgetfs: bound to dummy_udc driver
usb 1-1: new full-speed USB device number 2 using dummy_hcd
gadgetfs: connected
gadgetfs: disconnected
gadgetfs: connected
Hi!
I've got the following report while fuzzing the kernel with syzkaller.
On commit e19b205be43d11bff638cad4487008c48d21c103 (4.14-rc2).
gadgetfs: bound to dummy_udc driver
usb 1-1: new full-speed USB device number 2 using dummy_hcd
gadgetfs: connected
gadgetfs: disconnected
gadgetfs: connected
On Wed, 27 Sep 2017 10:35:51 +0200
Romain Izard wrote:
> During backup mode, the contents of all registers will be cleared as the
> SoC will be completely powered down. For a product that boots on NAND
> Flash memory, the bootloader will obviously use the related controller
> to read the Flash an
2017-09-27 17:08 GMT+02:00 Boris Brezillon :
> On Wed, 27 Sep 2017 10:35:51 +0200
> Romain Izard wrote:
>
>> During backup mode, the contents of all registers will be cleared as the
>> SoC will be completely powered down. For a product that boots on NAND
>> Flash memory, the bootloader will obviou
On 09/17/2017 at 09:32 AM, Andreas Hartmann wrote:
> Hello again!
>
> I can add now some more information about this problem:
>
> - I can see it w/ Fedora 26 boot medium, too.
> - I added an usb wireshark trace - hopefully this can be used to detect the
> problem.
It turned out, that the device
On Wed, Sep 27, 2017 at 12:15 AM, Oliver Neukum wrote:
> Am Dienstag, den 26.09.2017, 08:19 -0700 schrieb Doug Anderson:
>>
>> I know that for at least some of the adapters in the CDC Ethernet
>> blacklist it was claimed that the CDC Ethernet support in the adapter
>> was kinda broken anyway so th
On Mon, Sep 25, 2017 at 7:29 PM, Jaejoong Kim wrote:
> Hi,
>
> The below link will help.
>
> http://git.ideasonboard.org/uvc-gadget.git
> https://lwn.net/Articles/203924/
>
> Jaejoong
>
Thanks for the reply. But I need some clarification. Usually when a
character device (which as far as I unders
Make this const as it is only stored in the const field of a structure
video_device in the file referencing it. Make the declaration const too.
Done using Coccinelle.
Signed-off-by: Bhumika Goyal
---
drivers/usb/gadget/function/uvc_v4l2.c | 2 +-
drivers/usb/gadget/function/uvc_v4l2.h | 2 +-
2
This linksys dongle by default comes up in cdc_ether mode.
This patch allows r8152 to claim the device:
Bus 002 Device 002: ID 13b1:0041 Linksys
Signed-off-by: Grant Grundler
---
drivers/net/usb/cdc_ether.c | 10 ++
drivers/net/usb/r8152.c | 2 ++
2 files changed, 12 insertions(+
Hi Manu,
On Wed, Sep 27, 2017 at 02:29:10PM +0530, Manu Gautam wrote:
> VBUS signal coming from PHY must be asserted in device for
> controller to start operation or assert pull-up. For some
> platforms where VBUS line is not connected to PHY there is
> HS_PHY_CTRL register in QSCRATCH wrapper tha
On Wed, Sep 27, 2017 at 02:29:09PM +0530, Manu Gautam wrote:
> QMP V3 USB3 PHY is a DP USB combo PHY with
> dual RX/TX lanes to support type-c. There is a
> separate block DP_COM for configuration related
> to type-c or DP. Add support for dp_com region
> and secondary rx/tx lanes initialization.
On Wed, Sep 27, 2017 at 10:57:41AM -0700, Jack Pham wrote:
> Hi Manu,
>
> On Wed, Sep 27, 2017 at 02:29:10PM +0530, Manu Gautam wrote:
> > VBUS signal coming from PHY must be asserted in device for
> > controller to start operation or assert pull-up. For some
> > platforms where VBUS line is not c
On Wed, 27 Sep 2017 11:03:41 +0300
Mathias Nyman wrote:
> Ok, please let me know which register you refer to, I'd like to get this
> fixed as soon as possible.
> Based on what you say I suspect that you talk about the SBRN (Serial bus
> release number).
>
> The early xhci 1.1 spec that was use
Treat the ef/04/01 interface class/subclass/protocol combination used
by the Novatel Verizon USB730L (1410:9030) as a possible RNDIS
interface.
T: Bus=01 Lev=02 Prnt=02 Port=01 Cnt=02 Dev#= 17 Spd=480 MxCh= 0
D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 3
P: Vendor=1410 ProdID=9
Hi,
On Wed, Sep 27, 2017 at 10:28 AM, Grant Grundler wrote:
> This linksys dongle by default comes up in cdc_ether mode.
> This patch allows r8152 to claim the device:
>Bus 002 Device 002: ID 13b1:0041 Linksys
>
> Signed-off-by: Grant Grundler
> ---
> drivers/net/usb/cdc_ether.c | 10 ++
Hi Doug!
On Wed, Sep 27, 2017 at 4:47 PM, Doug Anderson wrote:
> Hi,
>
> On Wed, Sep 27, 2017 at 10:28 AM, Grant Grundler
> wrote:
>> This linksys dongle by default comes up in cdc_ether mode.
>> This patch allows r8152 to claim the device:
>>Bus 002 Device 002: ID 13b1:0041 Linksys
>>
>> S
Remove dummy clocks for usb wakeup and add optional ones for
mcu_bus and dma_bus bus.
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/usb/mediatek,mtu3.txt | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/mediatek
Remove optional pinctrls due to using FORCE/RG_IDDIG to implement
manual switch function.
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/usb/mediatek,mtu3.txt |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/mediate
Add a new optional property to disable u3ports
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/usb/mediatek,mtu3.txt |2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
b/Documentation/devicetree/bindings/usb/mediatek,mtu
2017-09-28 2:07 GMT+09:00 Rail Shafigulin :
> On Mon, Sep 25, 2017 at 7:29 PM, Jaejoong Kim wrote:
>> Hi,
>>
>> The below link will help.
>>
>> http://git.ideasonboard.org/uvc-gadget.git
>> https://lwn.net/Articles/203924/
>>
>> Jaejoong
>>
>
> Thanks for the reply. But I need some clarification.
Hi Jack,
On 9/28/2017 12:46 AM, Jack Pham wrote:
> On Wed, Sep 27, 2017 at 10:57:41AM -0700, Jack Pham wrote:
>> Hi Manu,
>>
>> On Wed, Sep 27, 2017 at 02:29:10PM +0530, Manu Gautam wrote:
>>> VBUS signal coming from PHY must be asserted in device for
>>> controller to start operation or assert p
Am Mittwoch, den 27.09.2017, 20:49 +1000 schrieb Christian Bullow:
> Hi Oliver thank you for your reply.
>
> Apologies for now replying from gmail. I'm being told my crjb.net
> address is failing SPF and that I have to shoehorn this email into
> plain-text for you. Here we go :)
>
> I must corr
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