Hi,
Alan Stern writes:
>> > Index: usb-4.x/drivers/usb/gadget/legacy/inode.c
>> > ===
>> > --- usb-4.x.orig/drivers/usb/gadget/legacy/inode.c
>> > +++ usb-4.x/drivers/usb/gadget/legacy/inode.c
>> > @@ -1126,7 +1126,7 @@ ep0_write (s
2016-12-27 13:16 GMT+01:00 Baolin Wang :
> Hi,
>
> On 27 December 2016 at 19:11, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Baolin Wang writes:
>>> Hi,
>>>
>>> On 27 December 2016 at 18:52, Janusz Dziedzic
>>> wrote:
2016-12-26 9:01 GMT+01:00 Baolin Wang :
> On some platfroms(like x86 platfor
2016-12-27 12:05 GMT+01:00 Felipe Balbi :
> Hi,
>
> Lu Baolu writes:
>> On 12/26/2016 04:01 PM, Baolin Wang wrote:
>>> On some platfroms(like x86 platform), when one core is running the USB
>>> gadget
>>> irq thread handler by dwc3_thread_interrupt(), meanwhile another core also
>>> can
>>> resp
Hi,
Janusz Dziedzic writes:
On some platfroms(like x86 platform), when one core is running the USB
gadget
irq thread handler by dwc3_thread_interrupt(), meanwhile another core also
can
respond other interrupts from dwc3 controller and modify the event buffer
by
>
Hi There,
Not sure if this might need to go to networking instead.
The issue is related to getting USB tethering for my phone.
It works with a galaxy-s4, but not with oneplus-3t. I think
it's a kernel related bug. All log excerpts are from my
linux-laptop to which i plug the phone via USB.
A
From: Colin Ian King
trivial fix to typo in dev_dbg message
Signed-off-by: Colin Ian King
---
drivers/usb/renesas_usbhs/mod_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/renesas_usbhs/mod_host.c
b/drivers/usb/renesas_usbhs/mod_host.c
index 165e81b..dfb
In the case of ULPI devices, we want to be able to load the
driver before registering the device so that we don't get stuck
in a loop waiting for the phy module to appear and failing usb
controller probe. Currently we request the ulpi module via the
ulpi ids, but in the DT case we might need to req
The MSM chipidea wrapper has two bits that are used to reset the
first or second phy. Add support for these bits via the reset
controller framework, so that phy drivers can reset their
hardware at the right time during initialization.
Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Signed-off-by: St
The high-speed phy on qcom SoCs is controlled via the ULPI
viewport.
Cc: Kishon Vijay Abraham I
Cc:
Acked-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/phy/qcom,usb-hs-phy.txt| 78 +++
drivers/phy/Kconfig| 8 +
drivers/phy/M
The HSIC USB controller on qcom SoCs has an integrated all
digital phy controlled via the ULPI viewport.
Cc: Kishon Vijay Abraham I
Acked-by: Rob Herring
Cc:
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/phy/qcom,usb-hsic-phy.txt | 65 +
drivers/phy/Kconfig
If the phy supports it, call phy_set_mode() to pull up D+ when
required by setting the mode to PHY_MODE_USB_DEVICE. If we want
to remove the pullup, set the mode to PHY_MODE_USB_HOST.
Cc: Peter Chen
Cc: Greg Kroah-Hartman
Signed-off-by: Stephen Boyd
---
drivers/usb/chipidea/udc.c | 10
If something fails in ci_hdrc_add_device() due to probe defer, we
shouldn't print an error message. Be silent in this case as we'll
try probe again later.
Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Signed-off-by: Stephen Boyd
---
drivers/usb/chipidea/ci_hdrc_msm.c | 3 ++-
1 file changed, 2 i
The msm chipidea controller uses two main clks, an AHB clk to
read/write the MMIO registers and a core clk called the system
clk that drives the controller itself. Add support for these clks
as they're required in all designs.
Also add support for an optional third clk that we need to turn
on to r
The core framework already handles setting this parameter with a
platform quirk. Add the appropriate flag so that we always set
AHBBURST to 0. Technically DT should be doing this, but we always
do it for msm chipidea devices so setting the flag in the driver
works just as well. If the burst needs t
The two extcon notifiers are almost the same except for the
variable name for the cable structure and the id notifier inverts
the cable->state logic. Make it the same and replace two
functions with one to save some lines. This also makes it so that
the id cable state is true when the id pin is pull
We're not properly marking the glue layer/wrapper device as
runtime active, so runtime PM believes that the hardware state is
inactive when we call pm_runtime_enable() in this driver. This
causes a problem when the glue layer has a power domain
associated with it, because runtime PM will go and dis
When the RESET bit is set in the USBCMD register it resets quite
a few of the wrapper's registers to their reset state. This
includes the GENCONFIG and GENCONFIG2 registers. Currently this
is done by the usb phy and ehci-msm drivers writing into the
controller wrapper's MMIO address space. Let's co
The MSM_USB_BASE macro trick is not very clear, and we're using
it for only one register write so let's just move to using
hw_write_id_reg() and passing the ci pointer instead. That
clearly shows what offset we're using and avoids needing to
include the msm_hsusb_hw.h file when we're going to delet
If two devices are probed with this same driver, they'll share
the same platform data structure, while the chipidea core layer
writes and modifies it. This can lead to interesting results
especially if one device is an OTG type chipidea controller and
another is a host. Let's create a copy of this
Some phys for the chipidea controller are controlled via the ULPI
viewport. Add support for the ULPI bus so that these sorts of
phys can be probed and read/written automatically without having
to duplicate the viewport logic in each phy driver.
Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Cc: Hei
From: Peter Chen
At some situations, the vbus may already be there before starting
gadget. So we need to check vbus event after switch to gadget in
order to handle missing vbus event. The typical use cases are plugging
vbus cable before driver load or the vbus has already been there
after stoppin
We need to pick the correct phy at runtime based on how the SoC
has been wired onto the board. If the secondary phy is used, take
it out of reset and mux over to it by writing into the TCSR
register. Make sure to do this on reset too, because this
register is reset to the default value (primary phy
The CI_HDRC_CONTROLLER_STOPPED_EVENT may want to call sleeping
APIs similar to how _gadget_stop_activity() may. Let's drop the
lock across the event so that glue drivers can make sleeping
calls.
Cc: Peter Chen
Cc: Greg Kroah-Hartman
Signed-off-by: Stephen Boyd
---
drivers/usb/chipidea/udc.c |
The ULPI phy on qcom platforms needs to be initialized and
powered on after a USB reset and before we toggle the run/stop
bit. Otherwise, the phy locks up and doesn't work properly. Hook
the phy initialization into the RESET event and the phy power off
into the STOPPED event.
Acked-by: Peter Chen
The ULPI bus can be built as a module, and it will soon be
calling these functions when it supports probing devices from DT.
Export them so they can be used by the ULPI module.
Acked-by: Rob Herring
Cc:
Signed-off-by: Stephen Boyd
---
drivers/of/device.c | 2 ++
1 file changed, 2 insertions(+)
The state of USB ChipIdea support on Qualcomm's platforms is not great.
The DT description of these devices requires up to three different nodes
for what amounts to be the same hardware block, when there should really
only be one. Furthermore, the "phy" driver that is in mainline (phy-msm-usb.c)
du
The qcom HSIC ULPI phy doesn't have any bits set in the vendor or
product ID registers. This makes it impossible to make a ULPI
driver match against the ID registers. Add support to discover
the ULPI phys via DT help alleviate this problem. In the DT case,
we'll look for a ULPI bus node underneath
We're currently emulating the vbus and id interrupts in the OTGSC
read API, but we also need to make sure that if we're handling
the events with extcon that we don't enable the interrupts for
those events in the hardware. Therefore, properly emulate this
register if we're using extcon, but don't en
With the id and vbus detection done via extcon we need to make
sure we poll the status of OTGSC properly by considering what the
extcon is saying, and not just what the register is saying. Let's
move this hw_wait_reg() function to the only place it's used and
simplify it for polling the OTGSC regis
The chipidea/udc.c file sends a CI_HDRC_CONTROLLER_RESET_EVENT to
the wrapper drivers when it calls hw_device_reset(), but that
function is not called from chipidea/host.c. And the udc.c file
sends the CI_HDRC_CONTROLLER_STOPPED_EVENT but the host.c file
doesn't do anything.
The intent of the rese
We don't call hw_device_reset() with the ci->lock held, so it
doesn't seem like this lock here is protecting anything. Let's
just remove it. This allows us to call sleeping functions like
phy_init() from within the CI_HDRC_CONTROLLER_RESET_EVENT hook.
Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
The ULPI phy on qcom platforms needs to be initialized and
powered on after a USB reset and before we toggle the run/stop
bit. Otherwise, the phy locks up and doesn't work properly.
Therefore, add a flag to skip any phy power management in the
core layer, leaving it up to the glue driver to manage.
> -Original Message-
> From: Felipe Balbi [mailto:ba...@kernel.org]
> Sent: Tuesday, December 27, 2016 3:33 AM
> To: John Youn ; linux-usb@vger.kernel.org
> Cc: John Youn ; Sriram Dash
> ; Baolin Wang ; Arnd
> Bergmann
> Subject: Re: [PATCH v2] usb: dwc3: pci: Add "linux,sysdev_is_parent"
> -Original Message-
> From: Felipe Balbi [mailto:ba...@kernel.org]
> Sent: Tuesday, December 27, 2016 3:37 AM
> To: John Youn ; John Youn
> ; linux-usb@vger.kernel.org
> Subject: Re: [PATCH 0/9] usb: dwc2: Fix checkpatch issues
>
>
> Hi John,
>
> John Youn writes:
> > The dwc2 driver
> -Original Message-
> From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
> ow...@vger.kernel.org] On Behalf Of Felipe Balbi
> Sent: Wednesday, December 28, 2016 8:19 AM
> To: Janusz Dziedzic
> Cc: Lu Baolu ; Baolin Wang
> ; Greg KH ; USB
> ; LKML ; Linaro
> Kernel Mailman List ; M
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