On Fri, Oct 21, 2016 at 04:49:07PM -0400, Alan Stern wrote:
> The UHCI controllers in Intel chipsets rely on a platform-specific
> non-PME mechanism for wakeup signalling. They can generate wakeup
> signals even though they don't support PME.
>
> We need to let the USB core know this so that it w
On Fri, Oct 21, 2016 at 05:04:06PM +0200, Johan Hovold wrote:
> Hi Greg,
>
> Here are some fixes for 4.9-rc2. Details below.
>
> Thanks,
> Johan
>
>
> The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
>
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available
On Sat, Oct 22, 2016 at 03:24:56PM +0100, Aidan Thornton wrote:
> On 19 Oct 2016 09:42, "Johan Hovold" wrote:
> >
> > On Wed, Oct 19, 2016 at 09:26:39AM +0200, Grigori Goronzy wrote:
> > > So let's just undo the change to the initialization sequence and get
> > > this merged. Then we can tune or
No functional changes, this just gives names to some registers and USB
requests based on Grigori Goronzy's work and WinChipTech's Linux driver
(which reassuringly agree), then uses them in place of magic numbers.
This also renames the misnamed BREAK2 register (actually UART config)
Signed-off-by:
This is an attempt to clean-up and resubmit some patches by Grigori
Goronzy a few months back adding support for parity, frame length, and
2 stop bits to the CH340/1 driver and cleaning up some magic constants.
His later patches (for RTS/CTS hardware flow and other things) are not
included in this
Will probably be helpful if there are any more compatibility issues.
Signed-off-by: Aidan Thornton
---
drivers/usb/serial/ch341.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/serial/ch341.c b/drivers/usb/serial/ch341.c
index af9edbe..2597b83 100644
--- a/drivers/usb/serial/ch3
With the new reinitialization method, configuring parity, different
frame lengths and different stop bit settings should work as expected
on both CH340G and CH341A. Tested on a loopback-connected CH340G
with a logic analyzer in a number of different configurations.
Based on a patch by Grigori Goro
Changing the LCR register after initialization does not seem to be reliable
on all chips (particularly not on CH341A). Restructure initialization and
configuration to always reinit the chip on configuration changes instead and
pass the LCR register value directly to the initialization command.
(No
This removes 10 timer wakeups per second. I'm running this patch for
a while now and haven't spotted any adverse effects.
Signed-off-by: Lucas Stach
---
v2: Merge vendor AMD case with vendor Intel case, as requested by
Alan Stern.
---
drivers/usb/host/ehci-pci.c | 1 +
1 file changed, 1 inse
This merges the vendor NEC case with the INTEL and AMD one,
as those 3 do exactly the same thing: disabling of the IO
watchdog.
Signed-off-by: Lucas Stach
---
v2: New patch in v2.
---
drivers/usb/host/ehci-pci.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/usb/host/ehci-pci.c b/d
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