Hi,
Finally, I was able to test on v4.8-rc4
[ +0.018224] xhci_hcd :00:14.0: xHCI Host Controller
[ +0.16] xhci_hcd :00:14.0: new USB bus registered, assigned
bus number 2
[ +0.91] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
[ +0.05] usb usb2: New USB devi
Hi,
Finally, I was able to test another USB3 key (Sandisk 64Gb instead of
the previous Goodram 8Gb) :
Bus 002 Device 002: ID 0781:5590 SanDisk Corp.
... and unloading xhci_pci / xhci_hcd while letting the USB3 key plugged
then reloading xhci_pci / xhci_hcd is working fine. (Sorry, this is a
test
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Hello Alan, Ulf.
Sorry for the delayed reply. Last week was a sickly week for me.
On Tue, 2016-08-30 at 10:14 +0200, Ulf Hansson wrote:
> On 25 August 2016 at 19:17, Alan Stern wrote:
> > Ulf:
> >
> > Ritesh has collected logs showing that his Rea
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On Sun, 2016-09-04 at 17:02 +0530, Ritesh Raj Sarraf wrote:
> > Sorry for the delay! We have had some regressions for 4.8 rc1 in the
> > mmc block layer. Those problem should be resolved by now.
> >
> > By reading from the runtime PM issues you have
On Sun, Sep 04, 2016 at 11:47:42AM +0200, kulamfm wrote:
> Hi,
>
> Finally, I was able to test another USB3 key (Sandisk 64Gb instead of
> the previous Goodram 8Gb) :
>
> Bus 002 Device 002: ID 0781:5590 SanDisk Corp.
>
> ... and unloading xhci_pci / xhci_hcd while letting the USB3 key plugged
>
On Sun, 4 Sep 2016, Ritesh Raj Sarraf wrote:
> > This issue has been around with previous kernels too.
> >
> > > Perhaps you can run a test on a 4.8 rc4 kernel, just to double check.
> > > The 4.8 rc4, contains the following fixes in the mmc block layer.
> > >
> > > commit 7afafc8a44bf ("block:
USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related
dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs.
Expose these clocks to DT and comment out in clk driver.
Signed-off-by: Jerome Brunet
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/gxbb.h | 1
From: Jerome Brunet
Add compatible strings for amlogic Meson8b and GXBB SoCs with the
corresponding configuration parameters.
Signed-off-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
drivers/usb/dwc2/platform.c
This series adds initial support for the DWC2 USB controllers and Meson
specific USB PHYs found in Meson8b and GXBB SoCs, which means:
- new DWC2 bindings and platform specific core configuration
- a PHY driver supporting the USB2 PHY on Meson8b and GXBB SoCs
The first DWC2 controller is usually c
From: Jerome Brunet
Enable both gxbb USB controller and add a 5V regulator for the OTG port
VBUS
Signed-off-by: Jerome Brunet
Signed-off-by: Martin Blumenstingl
---
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 29
1 file changed, 29 insertions(+)
diff --git a/a
Add the nodes for the dwc2 USB controller and the related USB PHYs.
Currently we force usb0 to host mode because OTG is currently not
working in our PHY driver.
Signed-off-by: Jerome Brunet
Signed-off-by: Martin Blumenstingl
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 52 +
This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.
Signed-off-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
---
drivers/phy/Kconfig | 11 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-meson-usb2.c | 299 +++
3
Add the documentation for the bindings for the Meson8b and GXBB USB2
PHYs.
Signed-off-by: Martin Blumenstingl
---
.../devicetree/bindings/phy/meson-usb2-phy.txt | 27 ++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/meson-usb2-
Enable both gxbb USB controller and add a 5V regulator for the OTG port
VBUS
Signed-off-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
---
.../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/aml
Hi Martin,
Am 04.09.2016 um 23:31 schrieb Martin Blumenstingl:
> Add the nodes for the dwc2 USB controller and the related USB PHYs.
> Currently we force usb0 to host mode because OTG is currently not
> working in our PHY driver.
>
> Signed-off-by: Jerome Brunet
> Signed-off-by: Martin Blumensti
Hi Greg,
Thanks for quick reply.
Actually we are now only planing to do such device which support H264,
but we wonder if the kernel USB host stack can support such case.
Thanks!
On Thu, Sep 1, 2016 at 1:57 PM, Greg KH wrote:
> On Thu, Sep 01, 2016 at 11:31:20AM +0800, Tang Jianqiang wrote
Some resources, such as IPPC register etc, shared with device
driver are moved into common glue layer when xHCI driver is the
host side of dual-role mode and they should be changed as optional
properties if they are required ones before. For clarity, add
a new part of binding to support host side o
This patch adds support for the MediaTek USB3 controller
integrated into MT8173. It can be configured as Dual-Role
Device (DRD), Peripheral Only and Host Only (xHCI) modes.
Signed-off-by: Chunfeng Yun
---
drivers/usb/Kconfig|2 +
drivers/usb/Makefile |1 +
d
add a DT binding doc for MediaTek USB3 DRD driver
Signed-off-by: Chunfeng Yun
Acked-by: Rob Herring
---
.../devicetree/bindings/usb/mt8173-mtu3.txt| 87
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
dif
Make IPPC register optional to support host side of dual-role mode,
due to it is moved into common glue layer for simplification.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c | 36 +---
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git
USB3 DRD driver is added for MT8173-EVB, and xHCI driver
becomes its subnode
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 46 +--
arch/arm64/boot/dts/mediatek/mt8173.dtsi| 29 +
2 files changed, 66 insertions(+), 9
>From 99e428a1808c8ca91ff473d487b52ca5d355d875 Mon Sep 17 00:00:00 2001
From: Chunfeng Yun
Date: Mon, 5 Sep 2016 10:27:07 +0800
Subject: [PATCH, v6 0/5] Add MediaTek USB3 DRD Driver
These patches introduce the MediaTek USB3 dual-role controller
driver.
The driver can be configured as Dual-Role D
On Fri, Sep 02, 2016 at 06:03:06PM -0700, Stephen Boyd wrote:
> On Thu, Sep 1, 2016 at 8:17 PM, Peter Chen wrote:
> > On Wed, Aug 31, 2016 at 05:40:24PM -0700, Stephen Boyd wrote:
> >>
> >>
> >> if (cable->state)
> >> - val |= OTGSC_ID;
> >> +
On Fri, Sep 02, 2016 at 08:20:35PM +0200, Stefan Wahren wrote:
> Hi Peter,
>
> > Stefan Wahren hat am 25. August 2016 um 19:17
> > geschrieben:
> >
> >
> > Hi,
> >
> > > Peter Chen hat am 25. August 2016 um 11:16
> > > geschrieben:
> > >
> > >
> > > On Thu, Aug 25, 2016 at 08:27:03AM +0200,
On Fri, Sep 02, 2016 at 06:42:43PM +0200, Clemens Gruber wrote:
> On Fri, Sep 02, 2016 at 09:55:52AM +0800, Peter Chen wrote:
> > Do you have other 5V to USB_H1_VBUS? USB PHY needs 5V input voltage
> > as the source for USB LDO (3.0v), either from OTG or Host 1. I suspect
> > the lower vbus voltage
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