Hello,
On 2014-05-13 08:21, Vivek Gautam wrote:
On Mon, May 12, 2014 at 10:19 PM, Kamil Debski wrote:
> When the driver is removed s3c_hsotg_phy_disable is called three times
> instead of once. This results in decreasing of the phy reference counter
> below zero and thus consecutive inserts of
On Tue, May 13, 2014 at 12:13 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 13 May 2014 11:37 AM, Vivek Gautam wrote:
>> Hi Kishon,
>>
>>
>> On Mon, May 12, 2014 at 6:33 PM, Kishon Vijay Abraham I
>> wrote:
>>> Hi Gautam,
>>>
>>> On Friday 09 May 2014 07:27 PM, Vivek Gautam wrote:
On Mon, May 12, 2014 at 04:06:16PM -0400, Alan Stern wrote:
> On Mon, 12 May 2014, Maxime Ripard wrote:
>
> > From: Boris BREZILLON
> >
> > On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
> > be deasserted for the EHCI block to be usable.
> >
> > Add support for an opt
On 13/05/2014 07:53, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Sunday 11 May 2014 11:47 PM, Thomas Petazzoni wrote:
>> From: Gregory CLEMENT
>>
>> The Armada 375 SoC comes with an USB2 host and device controller and
>> an USB3 controller. The USB cluster control register allows to manage
>> comm
On Sat, 2014-05-10 at 17:41 +0200, Bjørn Mork wrote:
> Split out the part of setup dealing with updating the rx_max
> and tx_max buffer sizes so that this code can be reused for
> dynamically updating the limits.
>
> Signed-off-by: Bjørn Mork
> ---
> drivers/net/usb/cdc_ncm.c | 81
> +++
On 05/12/2014 08:36 PM, Thomas Petazzoni wrote:
Dear Mathias Nyman,
On Mon, 12 May 2014 20:24:45 +0300, Mathias Nyman wrote:
+int xhci_mvebu_mbus_init_quirk(struct platform_device *pdev)
+{
+ struct resource *res;
+ void __iomem *base;
+ const struct mbus_dram_target_info *dr
From: Boris BREZILLON
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
ar
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dt
Hi everyone,
This patchset adds support for the USB controllers found in the
Allwinner A31.
While the design is similar to the earlier Allwinner SoCs that are
already supported, a few details here and there change, like the fact
that the PHYs now have one clock per phy, while it used to be only o
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
Documentation/devicetree/bindings/usb/usb-ohci.txt | 1 +
d
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Acked-by: Mike Turquette
---
drivers/clk/sunxi/clk-sunxi.c | 6
From: Boris BREZILLON
On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
be deasserted for the EHCI block to be usable.
Add support for an optional reset controller that will be deasserted on
power off and asserted on power on.
Signed-off-by: Boris BREZILLON
Signed-off-b
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 42 +++
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 33 +
Add sw_babble_control() logic to differentiate between transient
babble and real babble condition. Also add the SW babble control
register definitions.
Babble control register logic is implemented in the latest
revision of AM335x.
Signed-off-by: George Cherian
---
drivers/usb/musb/musb_dsps.c |
Find whether we are running on newer silicon. The babble control
register reads 0x4 by default in newer silicon as opposed to 0
in old versions of AM335x. Based on this enable the sw babble
control logic.
Signed-off-by: George Cherian
---
drivers/usb/musb/musb_dsps.c | 34 +++
Currently musb_platform_reset() is only used by dsps.
In case of BABBLE interrupt for other platforms the musb_platform_reset()
is a NOP. In such situations no need to re-initialize the endpoints.
Also in the latest silicon revision of AM335x, we do have a babble recovery
mechanism without resetti
Series add support for SW babble control logic found in
new silicon versions of AM335x. Runtime differentiation of
silicon version is done by checking the BABBLE_CTL register.
For newer silicon the register default value read is 0x4 and
for older versions its 0x0.
Patch 1 -> Convert recover work
For DSPS platform usb_phy_vbus(_off/_on) are NOPs.
So during musb_platform_reset() call usb_phy(_shutdown/_init)
Signed-off-by: George Cherian
---
drivers/usb/musb/musb_dsps.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb
During babble condition both first disconnect of devices are
initiated. Make sure MUSB controller is reset and re-initialized
after all disconnects.
To acheive this schedule a delayed work for babble rrecovery.
While at that convert udelay to usleep_range.
Refer Documentation/timers/timers-howto.
Dear All - in general,
@Felipe - in particular,
I would like to ask your opinion on rearranging the way the source code files
are located in the drivers/usb/gadget directory.
These are the reasons for doing such a change:
- there are ~130 source code files already in a clean tree
- when all gad
Oliver Neukum writes:
> On Sat, 2014-05-10 at 17:41 +0200, Bjørn Mork wrote:
>> Split out the part of setup dealing with updating the rx_max
>> and tx_max buffer sizes so that this code can be reused for
>> dynamically updating the limits.
>>
>> Signed-off-by: Bjørn Mork
>> ---
>> drivers/net/
On Tue, 2014-05-13 at 10:49 +0200, Bjørn Mork wrote:
> Oliver Neukum writes:
>
> > On Sat, 2014-05-10 at 17:41 +0200, Bjørn Mork wrote:
> >> + /* clamp new_rx to sane values */
> >> + min = min_t(u32, USB_CDC_NCM_NTB_MIN_IN_SIZE,
> >> le32_to_cpu(ctx->ncm_parm.dwNtbInMaxSize));
> >> + max =
The drivers/usb/gadget directory contains many files.
Files which are related can be distributed into separate directories.
This patch moves the USB functions implementations into a separate directory.
Signed-off-by: Andrzej Pietrasiewicz
---
drivers/usb/gadget/Makefile|
The drivers/usb/gadget directory contains many files.
Files which are related can be distributed into separate directories.
This patch moves the legacy gadgets (i.e. those not using configfs)
into a separate directory.
Signed-off-by: Andrzej Pietrasiewicz
---
drivers/usb/gadget/Kconfig
Dear All - in general,
@Felipe - in particular,
[This is a resent version generated with git format-patch -M90%]
I would like to ask your opinion on rearranging the way the source code files
are located in the drivers/usb/gadget directory.
These are the reasons for doing such a change:
- there
The drivers/usb/gadget directory contains many files.
Files which are related can be distributed into separate directories.
This patch moves the UDC drivers into a separate directory.
Signed-off-by: Andrzej Pietrasiewicz
---
drivers/usb/gadget/Kconfig| 369 +--
W dniu 13.05.2014 11:09, Andrzej Pietrasiewicz pisze:
Dear All - in general,
@Felipe - in particular,
[This is a resent version generated with git format-patch -M90%]
3) Checkpatch issues about 2000 warnings on the 3 patches in this series.
I believe the vast majority of them are warnings on i
Oliver Neukum writes:
>> The reason I put that min_t() there instead was an attempt to deal with
>> the (not unlikely) event that some buggy device set dwNtbInMaxSize lower
>> than this required minimum value. We then have the choices:
>>
>> a) fail to support the buggy device
>> b) attempt t
Note: I am re-sending the mail, since I sent it privately to Bj*rn only, by
mistake. Sorry. And sorry also for continously mistyping your name: I would
like to learn writing it right! :)
I would also propose some polite warning message regarding what's happening.
Ok, I know it may simply be SPA
On 13/05/2014 10:06, Gregory CLEMENT wrote:
> On 13/05/2014 07:53, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Sunday 11 May 2014 11:47 PM, Thomas Petazzoni wrote:
>>> From: Gregory CLEMENT
>>>
>>> The Armada 375 SoC comes with an USB2 host and device controller and
>>> an USB3 controller. The U
Hi George,
On 05/13/2014 10:31 AM, George Cherian wrote:
> Series add support for SW babble control logic found in
> new silicon versions of AM335x. Runtime differentiation of
> silicon version is done by checking the BABBLE_CTL register.
> For newer silicon the register default value read is 0x4
Adding support to enable/disable VBUS controlled by a
regulator, to enable vbus supply on the port.
Signed-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usbdrd.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/
Based on 'next' branch of Kishon's phy tree (linux-phy).
Changes from v8:
- Moved out the bindings documentation for the PHY in a separate patch
to avoid checkpatch warnings.
Changes from v7:
- Providing an **alternative** approach for pmu-offset;
instead of getting it from DT, using offs
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Also, created a new header file in linux/mfd/syscon/ for
Exynos5 SoCs and put the required PMU offset definitions
Add necessary binding documentation for USB 3.0 DRD PHY present on
Exynos5 SoC series.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt| 47
1 file changed, 47 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.
Hi,
On Tue, May 13, 2014 at 12:30 PM, Marek Szyprowski
wrote:
> Hello,
>
>
> On 2014-05-13 08:21, Vivek Gautam wrote:
>>
>> On Mon, May 12, 2014 at 10:19 PM, Kamil Debski
>> wrote:
>> > When the driver is removed s3c_hsotg_phy_disable is called three times
>> > instead of once. This results in
Hi,
On 12/05/14 09:52, Krzysztof Opasiak wrote:
I agree that there was a possible off-by-one-error and thank you for
catching this I have missed it, but maybe it is not the best solution?
When you put '\0' sign to target[nmb-1] you are solving off by one
problem but you always lose the last sign
Hi,
On 12/05/14 09:58, Krzysztof Opasiak wrote:
Avoid calling usbg_read_string with a 40 byte long buffer, which in
turn is filled in
by usbg_read_buf which uses a maximum of USBG_MAX_LENGTH which is
256 bytes.
Signed-off-by: Philippe De Swert
---
src/usbg.c | 2 +-
1 file changed, 1 insert
Hello,
On 13/05/14 09:58, Krzysztof Opasiak wrote:
Please excuse me but I have missed this question yesterday.
No problem, I was helping a friend move so did not have time to answer
your other questions.;)
If you are talking about b returned from usbg_get_binding() don't be
afraid because
On Tue, 2014-05-13 at 11:25 +0200, Bjørn Mork wrote:
> Oliver Neukum writes:
> Yes, I agree. Will change this. Let's try to go for b) then. I.e.
>
> min = USB_CDC_NCM_NTB_MIN_IN_SIZE;
> max = min_t(u32, CDC_NCM_NTB_MAX_SIZE_RX,
> le32_to_cpu(ctx->ncm_parm.dwNtbInMaxSize));
>
On Tue, May 13, 2014 at 10:19:27AM +0800, Peter Chen wrote:
> the user should only select it when the board supports HNP and SRP,
> it should NOT be selected if the board only supports dual-role
> switch through ID pin.
>
> There is a discussion for it:
> http://marc.info/?l=linux-arm-kernel&m=139
On 5/13/2014 3:16 PM, Daniel Mack wrote:
Hi George,
On 05/13/2014 10:31 AM, George Cherian wrote:
Series add support for SW babble control logic found in
new silicon versions of AM335x. Runtime differentiation of
silicon version is done by checking the BABBLE_CTL register.
For newer silicon the
On 05/13/2014 01:57 PM, George Cherian wrote:
> On 5/13/2014 3:16 PM, Daniel Mack wrote:
>> On 05/13/2014 10:31 AM, George Cherian wrote:
>>> Series add support for SW babble control logic found in
>>> new silicon versions of AM335x. Runtime differentiation of
>>> silicon version is done by checkin
On Thu, May 8, 2014 at 9:08 PM, Dan Williams wrote:
> On Wed, 2014-05-07 at 15:30 +0530, Suresh Kumar N. wrote:
>> On Tue, May 6, 2014 at 9:42 PM, Dan Williams wrote:
>> > On Tue, 2014-05-06 at 14:27 +0530, Suresh Kumar N. wrote:
>> >> On Mon, May 5, 2014 at 8:38 PM, Dan Williams wrote:
>> >> >
Hi,
> -Original Message-
> From: Philippe De Swert [mailto:philippedesw...@gmail.com]
>
> You mean something like this?
>
> diff --git a/src/usbg.c b/src/usbg.c
> index 521513d..3774a6d 100644
> --- a/src/usbg.c
> +++ b/src/usbg.c
> @@ -843,14 +843,14 @@ static int
> usbg_parse_config_bi
Hi,
this bug hits my system now a long time. I had found e.g. this
speedy kernel: [ 9575.033019] irq 16: nobody cared (try booting with the
"irqpoll" option)
speedy kernel: [ 9575.033022] Pid: 0, comm: swapper/0 Not tainted
3.7.10-1.1-desktop #1
speedy kernel: [ 9575.033023] Call Trace:
sp
On 5/13/2014 5:50 PM, Daniel Mack wrote:
On 05/13/2014 01:57 PM, George Cherian wrote:
On 5/13/2014 3:16 PM, Daniel Mack wrote:
On 05/13/2014 10:31 AM, George Cherian wrote:
Series add support for SW babble control logic found in
new silicon versions of AM335x. Runtime differentiation of
silic
Hi George,
On 05/13/2014 02:57 PM, George Cherian wrote:
> I never enabled the MUSB_BABBLE_SW_SESSION_CTRL in the MUSB_BABBLE_CTL reg.
> can you try with the following patch.
>
> diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c
> index 1ae6681..1160cd1 100644
> --- a/drive
Hi Daniel,
On 5/13/2014 6:44 PM, Daniel Mack wrote:
Hi George,
On 05/13/2014 02:57 PM, George Cherian wrote:
I never enabled the MUSB_BABBLE_SW_SESSION_CTRL in the MUSB_BABBLE_CTL reg.
can you try with the following patch.
diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps
On 05/13/2014 03:24 PM, George Cherian wrote:
> Basically, there are 2 types of babble conditions.
> 1) Transient babble condition - which could be recovered from without an
> IP reset .
> 2) Babble condition - which could be recovered from only by doing an IP
> reset.
Ok, thanks for the explana
Hi Balbi,
Do you have any comment for this patch?
Thanks
Jincan
On Wed, May 07, 2014 at 05:53:44PM -0400, Zhuang Jin Can wrote:
> A delayed status request may be queued before composite framework returns
> USB_GADGET_DELAYED_STATUS, because the thread queueing the request can run
> on a differen
This patch series fixes a number of issues found with coverity in libusbg
A pull request has also be made:
https://github.com/libusbg/libusbg/pull/4
This is the second version where we use a different fix for the readlink,
actually use the right USB_MAX_STR_LENGTH define. I also fixed an issue
I m
We probably need to check if we get valid attributes passed. Otherwise we will
try to dereference a NULL-pointer as the usb_config_attr will not be valid.
Signed-off-by: Philippe De Swert
---
src/usbg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/usbg.c b/src/usbg.c
i
Avoid calling usbg_read_string with a 40 byte long buffer, which in turn is
filled in
by usbg_read_buf which uses a maximum of USBG_MAX_STR_LENGTH which is 256 bytes.
Signed-off-by: Philippe De Swert
---
src/usbg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/usbg.c b
Readlink can return the total length of the buffer (here 4096), so we do not
want to dereference target[4096] as that would give an off by one error.
Signed-off-by: Philippe De Swert
---
src/usbg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/usbg.c b/src/usbg.c
index
We check if func is NULL, so if the allocation function failed we should
not dereference or handle it anymore, so we jump straight to the end.
Signed-off-by: Philippe De Swert
---
src/usbg.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/usbg.c b/src/usbg.c
index 66aa435..8ad6a9e 100644
On Tue, 13 May 2014, Pratyush Anand wrote:
> > The biggest bug may not be an obvious one. Suppose the lvstest driver
> > has been built into the kernel. When the kernel boots and the root
> > hubs are registered, what will prevent them all from binding to lvstest
> > instead of the normal hub dr
On Tue, 13 May 2014, Andrzej Pietrasiewicz wrote:
> Dear All - in general,
> @Felipe - in particular,
>
> I would like to ask your opinion on rearranging the way the source code files
> are located in the drivers/usb/gadget directory.
>
> These are the reasons for doing such a change:
>
> - the
On Tue, 13 May 2014, Maxime Ripard wrote:
> Hi everyone,
>
> This patchset adds support for the USB controllers found in the
> Allwinner A31.
>
> While the design is similar to the earlier Allwinner SoCs that are
> already supported, a few details here and there change, like the fact
> that the
On Tue, May 13, 2014 at 06:46:05AM -0700, Jim Davis wrote:
> Building with the attached random configuration file,
>
> drivers/usb/phy/phy-msm-usb.c: In function ‘msm_otg_read_dt’:
> drivers/usb/phy/phy-msm-usb.c:1461:2: error: implicit declaration of
> function ‘devm_reset_control_get’
> [-Werror
drivers/reset/core.c does not provide an empty
stub for cases when CONFIG_RESET_CONTROLLER isn't
enabled, which might break build of the MSM PHY
driver if that driver is enabled but
CONFIG_RESET_CONTROLLER isn't.
We make the driver depend on CONFIG_RESET_CONTROLLER
so we can never have such a case
Hi,
On Tue, May 13, 2014 at 09:45:51PM -0400, Zhuang Jin Can wrote:
> Hi Balbi,
>
> Do you have any comment for this patch?
do you have an easy test-case which I can use to validate on my end ?
--
balbi
signature.asc
Description: Digital signature
Please CC: your patches to the maintainer of the driver you are
changing.
On Tue, 13 May 2014, Dr. Werner Fink wrote:
> Hi,
>
> this bug hits my system now a long time. I had found e.g. this
>
> speedy kernel: [ 9575.033019] irq 16: nobody cared (try booting with the
> "irqpoll" option)
>
Hi,
On Tue, May 13, 2014 at 10:45:15AM +0200, Andrzej Pietrasiewicz wrote:
> Dear All - in general,
> @Felipe - in particular,
>
> I would like to ask your opinion on rearranging the way the source code files
> are located in the drivers/usb/gadget directory.
>
> These are the reasons for doing
On Tue, 13 May 2014, Felipe Balbi wrote:
> drivers/reset/core.c does not provide an empty
> stub for cases when CONFIG_RESET_CONTROLLER isn't
> enabled, which might break build of the MSM PHY
> driver if that driver is enabled but
> CONFIG_RESET_CONTROLLER isn't.
>
> We make the driver depend on
Hi,
On Fri, May 09, 2014 at 11:25:46AM +0530, Pratyush Anand wrote:
> On Tue, May 06, 2014 at 02:22:12PM +0800, Amit VIRDI wrote:
> > On 5/6/2014 12:56 AM, Felipe Balbi wrote:
> > >> I understand that enabling XferInProgress event for bulk/interrupt
> > >> >transfers will completely
> > >> >change
On Thu, May 08, 2014 at 03:52:17PM +0200, Arnd Bergmann wrote:
> The isp1301-omap driver cannot be built-in if the tps65010 driver
> is a module, otherwise we get a link error from the reference to
> the tps65010_set_vbus_draw function.
>
> There is already a hack in the driver to work around the
On Thu, May 08, 2014 at 03:52:18PM +0200, Arnd Bergmann wrote:
> Commit a27345434134 "usb: phy: msm: Use reset framework for LINK
> and PHY resets" introduced a mandatory call to reset_control_get
> into the msm usb phy driver, which means we have to add a Kconfig
> dependency on the API to avoid t
On Thu, May 08, 2014 at 03:52:19PM +0200, Arnd Bergmann wrote:
> If we build a kernel with PM_SUSPEND set and no PM_SLEEP,
> we get a build warning in the xhci-plat driver about unused
> functions.
>
> To fix this, use "#ifdef CONFIG_PM_SLEEP", like we do in most
> other drivers nowadays.
>
> Sig
On Tue, May 13, 2014 at 11:08:27AM -0400, Alan Stern wrote:
> Please CC: your patches to the maintainer of the driver you are
> changing.
>
> On Tue, 13 May 2014, Dr. Werner Fink wrote:
>
> > Hi,
> >
> > this bug hits my system now a long time. I had found e.g. this
> >
> > speedy kernel: [
CC-ing Mathias.
On Mon, 12 May 2014, Jorge wrote:
> [1.] One line summary of the problem:
> [Sony VAIO SVT13136CXS] usb2 port does not work.
>
> [2.] Full description of the problem/report:
> My laptop has two usb ports, one 2.0 and the other 3.0. The usb 2.0 port
> does nothing. It seems to ha
On Tue, May 13, 2014 at 10:05:34AM -0500, Felipe Balbi wrote:
> Hi,
>
> On Tue, May 13, 2014 at 09:45:51PM -0400, Zhuang Jin Can wrote:
> > Hi Balbi,
> >
> > Do you have any comment for this patch?
>
> do you have an easy test-case which I can use to validate on my end ?
The issue was reproduced
On Tue, May 13, 2014 at 11:13:58AM -0400, Alan Stern wrote:
> On Tue, 13 May 2014, Felipe Balbi wrote:
>
> > drivers/reset/core.c does not provide an empty
> > stub for cases when CONFIG_RESET_CONTROLLER isn't
> > enabled, which might break build of the MSM PHY
> > driver if that driver is enabled
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Acked-by: Mike Turquette
---
drivers/clk/sunxi/clk-sunxi.c | 6
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Acked-by: Alan Stern
---
Documentation/devicetree/bindings/usb/
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dt
From: Boris BREZILLON
On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
be deasserted for the EHCI block to be usable.
Add support for an optional reset controller that will be deasserted on
power off and asserted on power on.
Signed-off-by: Boris BREZILLON
Signed-off-b
Hi everyone,
This patchset adds support for the USB controllers found in the
Allwinner A31.
While the design is similar to the earlier Allwinner SoCs that are
already supported, a few details here and there change, like the fact
that the PHYs now have one clock per phy, while it used to be only o
From: Boris BREZILLON
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
ar
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 33 +
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 42 +++
On Tue, May 13, 2014 at 01:11:44PM +0200, Greg KH wrote:
> On Tue, May 13, 2014 at 10:19:27AM +0800, Peter Chen wrote:
> > the user should only select it when the board supports HNP and SRP,
> > it should NOT be selected if the board only supports dual-role
> > switch through ID pin.
> >
> > There
On Tuesday, May 13, 2014 8:30 AM, Felipe Balbi wrote:
>
> On Tue, May 13, 2014 at 11:13:58AM -0400, Alan Stern wrote:
> > On Tue, 13 May 2014, Felipe Balbi wrote:
> >
> > > drivers/reset/core.c does not provide an empty
> > > stub for cases when CONFIG_RESET_CONTROLLER isn't
> > > enabled, which m
Hi,
On Thu, May 08, 2014 at 03:03:07PM +0530, George Cherian wrote:
> Enabling the core interrupts in complete is too late for XHCI, and stops
> xhci from proper operation. So remove prepare and complete and disable/enable
isn't this a bug in xhci ? I mean the driver should make no assumption
as
On Tue, May 13, 2014 at 05:49:06PM +0200, Bird, Tim wrote:
> On Tuesday, May 13, 2014 8:30 AM, Felipe Balbi wrote:
> >
> > On Tue, May 13, 2014 at 11:13:58AM -0400, Alan Stern wrote:
> > > On Tue, 13 May 2014, Felipe Balbi wrote:
> > >
> > > > drivers/reset/core.c does not provide an empty
> > > >
Avoid that the ehci driver cause that the shared IRQ will disabled.
This behaviour was seen now over several kernel versions with the
00:1a.0 USB controller [0c03]: Intel Corporation 6 Series/C200 Series Chipset
Family USB Enhanced Host Controller #2 [8086:1c2d] (rev 05) (prog-if 20 [EHCI])
S
On Tue, 13 May 2014, Dr. Werner Fink wrote:
> OK ... the patch was changed as I had been told that I should do it this
> way. In my original code I simply use
>
> masked_status = status & (INTR_MASK | STS_FLR | STS_RECL);
>
> /* Shared IRQ? */
> if (!masked_status || unlikely(
Hi,
On Thu, May 08, 2014 at 03:03:03PM +0530, George Cherian wrote:
> Calculate the wrapper register offsets in a seperate function.
> Improve code readability, decrease the dwc3_probe() size.
>
> Signed-off-by: George Cherian
> ---
> drivers/usb/dwc3/dwc3-omap.c | 80
> +++
In order to reduce the interrupt times in the embedded system,
a receiving workqueue is introduced.
This modification also enhanced the overall throughput as the
benefits of reducing interrupt occurrence.
This work was derived from previous work:
u_ether: move hardware transmit to RX workqueue.
Wh
On Tue, 13 May 2014, Bird, Tim wrote:
> I don't think so. I haven't tested, but I believe the driver now relies
> on operational (not stub) resets. I think this comment is a bit off.
> I think it would be better to just say that the driver now depends on the
> reset sub-system, and thus needs th
On Tue, 13 May 2014, Dr. Werner Fink wrote:
> Avoid that the ehci driver cause that the shared IRQ will disabled.
> This behaviour was seen now over several kernel versions with the
>
> 00:1a.0 USB controller [0c03]: Intel Corporation 6 Series/C200 Series Chipset
> Family USB Enhanced Host Contr
On Tue, May 13, 2014 at 11:59:38AM -0400, Alan Stern wrote:
>
> What about something like this instead?
>
> masked_status = status & (INTR_MASK | STS_FLR);
>
> /* Shared IRQ? */
> if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
> + if (status &
Hi Maxime,
El 13/05/14 12:44, Maxime Ripard escribió:
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Acked-by: Mi
* Roger Quadros [140505 02:55]:
> Add USB pinmux information and USB modes
> for the USB controllers.
>
> CC: Benoît Cousson
> Reviewed-by: Felipe Balbi
> Signed-off-by: Roger Quadros
> ---
> arch/arm/boot/dts/dra7-evm.dts | 24
> 1 file changed, 24 insertions(+)
>
>
On Tue, 2014-05-13 at 17:58 +0530, Suresh Kumar N. wrote:
> On Thu, May 8, 2014 at 9:08 PM, Dan Williams wrote:
> > On Wed, 2014-05-07 at 15:30 +0530, Suresh Kumar N. wrote:
> >> On Tue, May 6, 2014 at 9:42 PM, Dan Williams wrote:
> >> > On Tue, 2014-05-06 at 14:27 +0530, Suresh Kumar N. wrote:
>
Hi,
On Tue, May 13, 2014 at 8:24 AM, George Cherian wrote:
> Hi Daniel,
>
>
> On 5/13/2014 6:44 PM, Daniel Mack wrote:
>>
>> Hi George,
>>
>> On 05/13/2014 02:57 PM, George Cherian wrote:
>>>
>>> I never enabled the MUSB_BABBLE_SW_SESSION_CTRL in the MUSB_BABBLE_CTL
>>> reg.
>>> can you try with
On Tuesday 13 May 2014 10:28:29 Felipe Balbi wrote:
> > diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
> > index 151901c..3473296 100644
> > --- a/drivers/usb/host/xhci-plat.c
> > +++ b/drivers/usb/host/xhci-plat.c
> > @@ -202,7 +202,7 @@ static int xhci_plat_remove(struct
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