Hi,
On 05/07/2014 05:50 AM, Maxime Ripard wrote:
> Hi everyone,
>
> This patchset adds support for the USB controllers found in the
> Allwinner A31.
>
> While the design is similar to the earlier Allwinner SoCs that are
> already supported, a few details here and there change, like the fact
> th
From: Alexej Starschenko
Adds product ID for the Novatel E371 PCI Express Mini Card.
$ lsusb
Bus 001 Device 024: ID 1410:9011 Novatel Wireless
$ usb-devices
T: Bus=01 Lev=01 Prnt=01 Port=03 Cnt=01 Dev#= 24 Spd=480 MxCh= 0
D: Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs= 1
P: Vendor=
Tony,
This patch will need to be updated for IRQ crossbar changes.
I will send a revised version of just this patch based on crossbar changes [1]
[1] - http://article.gmane.org/gmane.linux.documentation/23293
cheers,
-roger
On 05/05/2014 12:54 PM, Roger Quadros wrote:
> Add nodes for the Super
[Adding back the original Cc-List]
On 05/07/2014 10:33 AM, Hans de Goede wrote:
Hi Gregory,
Gregory CLEMENT free-electrons.com> writes:
This patch set adds the USB support for the Armada 38x Armada
375. These SoCs use an xHCI but still need specific initialization,
mainly to setup the window
Dear Alan Stern,
On Tue, 6 May 2014 10:30:57 -0400 (EDT), Alan Stern wrote:
> > err2:
> > - if (!IS_ERR(clk))
> > - clk_disable_unprepare(clk);
> > + usb_put_hcd(hcd);
>
> At this point, priv has just become a dangling pointer, because it
> points to something that was allocated a
Dear Andrew Lunn,
On Tue, 6 May 2014 15:33:41 +0200, Andrew Lunn wrote:
> > + priv->phy = devm_phy_get(&pdev->dev, "usb");
> > + if (!IS_ERR(priv->phy)) {
> > + err = phy_init(priv->phy);
> > + if (err)
> > + goto err2;
> > +
> > + err = phy_pow
Hi,
On 05/07/2014 11:21 AM, Sebastian Hesselbarth wrote:
> [Adding back the original Cc-List]
>
> On 05/07/2014 10:33 AM, Hans de Goede wrote:
>> Hi Gregory,
>>
>> Gregory CLEMENT free-electrons.com> writes:
>>
>>> This patch set adds the USB support for the Armada 38x Armada
>>> 375. These SoCs
A delayed status request may be queued before composite framework returns
USB_GADGET_DELAYED_STATUS, because the thread queueing the request can run
on a different core in parallel with the control request irq.
SETUP XferComplete IRQ fsg_main_thread
--
On Tue, May 6, 2014 at 9:42 PM, Dan Williams wrote:
> On Tue, 2014-05-06 at 14:27 +0530, Suresh Kumar N. wrote:
>> On Mon, May 5, 2014 at 8:38 PM, Dan Williams wrote:
>> > On Mon, 2014-05-05 at 11:07 +0530, Suresh Kumar N. wrote:
>> >> Hi,
>> >>
>> >> I am new to udev and device enumeration.
>> >
Dear Felipe Balbi,
On Tue, 6 May 2014 10:39:53 -0500, Felipe Balbi wrote:
> > config USB_EHCI_HCD
> > diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> > index 7530468c9a4f..7a8db7f7dc01 100644
> > --- a/drivers/usb/host/Makefile
> > +++ b/drivers/usb/host/Makefile
> > @@ -19,
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Use IRQ crossbar for interrupts.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
CC: Benoît Cousson
Reviewed-by: Felipe Balbi
Signed-off-by: Roger Quadros
---
Felipe, Gregory,
On Tue, 6 May 2014 02:14:00 +0200, Gregory CLEMENT wrote:
> +struct xhci_plat_priv {
> + struct clk *clk;
> +};
> +
> static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
> {
> /*
> @@ -38,7 +43,8 @@ static int xhci_plat_setup(struct usb_hcd *hcd)
Dear Bartlomiej Zolnierkiewicz,
On Tue, 06 May 2014 13:37:04 +0200, Bartlomiej Zolnierkiewicz wrote:
> > +config ARMADA375_USBCLUSTER_PHY
> > + def_bool y
> > + depends on OF
>
> Please limit this driver to Armada 375 or compile testing, i.e. add additional
>
> depends on (ARCH_MVEBU
Dear Andrew Lunn,
On Tue, 6 May 2014 15:54:27 +0200, Andrew Lunn wrote:
> > +enum {
> > + PHY_USB2 = 0,
> > + PHY_USB3 = 1,
> > +};
> > +
> > +struct armada375_cluster_phy {
> > + struct phy *phy;
> > + void __iomem *reg;
> > + bool enable;
> > + bool use_usb3;
>
> Hi Gregory
>
> ni
Dear Ezequiel Garcia,
On Tue, 6 May 2014 17:53:30 -0300, Ezequiel Garcia wrote:
> > +#define USB2_PHY_CONFIG_ENABLE BIT(0) /* active low */
> > +
>
> I still think it's more readable to use USB2_PHY_CONFIG_DISABLE.
> It's just a nitpick, though.
Yes, fixed.
> > +static int armada375_usb_phy_pr
On Wed, May 07, 2014 at 11:40:06AM +0200, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
>
> On Tue, 6 May 2014 15:33:41 +0200, Andrew Lunn wrote:
>
> > > + priv->phy = devm_phy_get(&pdev->dev, "usb");
> > > + if (!IS_ERR(priv->phy)) {
> > > + err = phy_init(priv->phy);
> > > + if (e
From: Dinh Nguyen
Even though the IP supports Descriptor DMA mode, it does not support SPLIT
transactions in this mode. So the driver, in its currently form, will not
support LS/FS devices when connected to a HS Hub if Descriptor DMA mode is
enabled.
So we should just default to disable descript
Hi,
On Wednesday 07 May 2014 09:20 AM, Maxime Ripard wrote:
> The USB phy controller in the A31 differs mostly from the older controllers
> because it has a clock dedicated for each phy, while the older ones were
> having
> a single clock for all the phys.
>
> Signed-off-by: Maxime Ripard
> ---
On 05/06/2014 02:41 PM, Ville Syrjälä wrote:
On Mon, May 05, 2014 at 12:32:22PM -0700, Julius Werner wrote:
Hmmm... very odd. I unfortunately don't have a machine that can easily
do S4 at hand, but I did test this on an IVB with XHCI_RESET_ON_RESUME
in S3 (essentially the same code path), and I
From: Dinh Nguyen
The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults
to 0x2000 or 8192 32-bit words. So the driver cannot just use the
From: Gregory CLEMENT
The Marvell Armada 38x SoCs contains two xHCI controllers. This commit
adds the Device Tree description of those interfaces at the SoC level,
and also enables the two USB3 ports on the Armada 385 DB platform and
one USB3 port on the Armada 385 RD platform.
Signed-off-by: Gr
From: Gregory CLEMENT
Some platforms (such as the Armada 38x ones) can gate the clock of
their USB controller. This patch adds the support for one clock in
xhci-plat, by enabling it during probe and disabling it on remove.
To achieve this, it adds a 'struct clk *' member in xhci_hcd. While
only
From: Gregory CLEMENT
On Armada 375, the USB cluster allows to control the cluster composed
of the USB2 and USB3 host controllers.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-375.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arc
From: Gregory CLEMENT
The Marvell Armada 375 SoCs contains one EHCI controller. This commit
adds the Device Tree description of this interfaces at the SoC level,
and also enables the USB2 port on the Armada 375 DB platform.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
---
ar
Hello,
This patch set adds the USB support for the Armada 38x and Armada 375
SOCs. These SoCs use an xHCI but still need specific initialization,
mainly to setup the MBus memory windows. They also have another USB
controller for EHCI, identical to the one used on other mvebu SOCs.
This series is
From: Gregory CLEMENT
The Marvell Armada 38x platform needs the xhci_mvebu driver enabled
for the xHCI USB hosts, so this commit enables the corresponding
Kconfig option in mvebu_v7_defconfig.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
---
arch/arm/configs/mvebu_v7_defconf
Commit 77dae54ab385033e488d8b07045bc7f8d931740f ('ARM: Kirkwood:
ehci-orion: Add device tree binding') added the Device Tree binding
for the ehci-orion driver. To achieve that with the irq, it used the
irq_of_parse_and_map() function when probed in DT-mode, and
platform_get_irq() when probed in non
From: Gregory CLEMENT
Sorting the headers in alphabetic order will help to reduce the conflict
when adding new headers later.
Signed-off-by: Gregory CLEMENT
Acked-by: Felipe Balbi
Signed-off-by: Thomas Petazzoni
---
drivers/usb/host/xhci-plat.c | 6 +++---
1 file changed, 3 insertions(+), 3
From: Gregory CLEMENT
Armada 375 comes with an USB2 host and device controller and an USB3
controller. The USB cluster control register allows to manage common
features of both USB controllers. This commit adds the Device Tree
binding documentation for this piece of hardware.
Signed-off-by: Greg
From: Gregory CLEMENT
The Marvell Armada 375 SoCs contain a xHCI controller. This commit
adds the Device Tree description of this interfaces at the SoC level,
and also enables the USB3 port on the Armada 375 DB platform.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
---
arch/
This commit updates the Device Tree binding documentation of
ehci-orion to take into account the fact that we can now optionally
pass a clock and a PHY reference.
Signed-off-by: Thomas Petazzoni
---
Documentation/devicetree/bindings/usb/ehci-orion.txt | 5 +
1 file changed, 5 insertions(+)
From: Gregory CLEMENT
In order to disable the clock in the ->remove() function, a call to
devm_clk_get() is being made, which further increases the reference
count of the clock.
In order to clean this up, a private structure holding a pointer to
the clock is added using the override mechanism pr
From: Gregory CLEMENT
The Armada 375 SoC comes with an USB2 host and device controller and
an USB3 controller. The USB cluster control register allows to manage
common features of both USB controllers.
This commit adds a driver integrated in the generic PHY framework to
control this USB cluster
From: Gregory CLEMENT
This commit extends the compatible string list of the xhci-platform
binding with the new "armada-375-xhci" and "armada-380-xhci"
compatible strings. It is used to describe the XHCI controller which
is available in the Armada 375 and 38x SoCs.
It also indicates that an optio
From: Gregory CLEMENT
This commit extends the ehci-orion so that it can optionally be passed
a reference to a PHY through the Device Tree. It will be useful for
the Armada 375 SoCs. If no PHY is provided then the behavior of the
driver is unchanged.
[Thomas: use devm_phy_optional_get() so that w
From: Gregory CLEMENT
The Marvell Armada 38x SoCs contains one EHCI controller. This commit
adds the Device Tree description of this interface at the SoC level,
and also enables the USB2 port on the Armada 385 DB platform.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
---
arc
From: Gregory CLEMENT
The Marvell Armada 38x platform needs the xhci_mvebu driver enabled
for the xHCI USB hosts, so this commit enables the corresponding
Kconfig option in multi_v7_defconfig.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
Cc: a...@kernel.org
Cc: Kevin Hilman
In preparation to the introduction of additional initialization steps
in ehci_orion_drv_probe(), we rename the error goto labels from err1,
err2 and err3 names to some more meaningful names.
Signed-off-by: Thomas Petazzoni
---
drivers/usb/host/ehci-orion.c | 18 +-
1 file changed
From: Gregory CLEMENT
This patch adds the selection of the config symbol needed to build the
USB3 support for Armada 38x into mvebu_v7_defconfig.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
---
arch/arm/mach-mvebu/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/
From: Gregory CLEMENT
The Armada 375 and 38x SoCs come with an XHCI controller that requires
some specific initialization related to the MBus windows
configuration. This patch adds the support for this special
configuration as an XHCI quirk executed during probe.
Two new compatible strings are a
From: Gregory CLEMENT
This patch add the selection of the config symbol to build the USB3
support for Armada 375.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
---
arch/arm/mach-mvebu/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/ar
Dear Andrew Lunn,
On Wed, 7 May 2014 15:21:50 +0200, Andrew Lunn wrote:
> > Thanks to devm_phy_optional_get(), the fact of not having a PHY in the
> > DT is not considered an error. So on any error from
> > devm_phy_optional_get() (including -EPROBE_DEFER), we simply bail out.
> > Does this looks
Hi,
Please ignore this patch.
It actually doesnot call sw_babble_ control() at all.
It should have.
Will post a fixed version.
On 5/7/2014 7:39 PM, George Cherian wrote:
Find whether we are running on newer silicon. The babble control
register reads 0x4 by default in newer silicon as opposed to
On Tue, 6 May 2014, Maxime Ripard wrote:
> From: Boris BREZILLON
>
> On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
> be deasserted for the EHCI block to be usable.
>
> Add support for an optional reset controller that will be deasserted on
> power off and asserted on
On 05/06/2014 11:43 PM, Felipe Balbi wrote:
Hi Mathias,
I was using (up until today) v3.13 (on my desktop PC) to test LPM
transitions against OMAP5. Since I was having some issues with U1 exit
after some 200 iterations I decided to make sure v3.15-rc4 would have
the same behavior but, to my surp
On Wed, 7 May 2014, Zhuang Jin Can wrote:
> A delayed status request may be queued before composite framework returns
> USB_GADGET_DELAYED_STATUS, because the thread queueing the request can run
> on a different core in parallel with the control request irq.
>
> SETUP XferComplete IRQ
On Wed, May 07, 2014 at 04:48:48PM +0300, Mathias Nyman wrote:
> On 05/06/2014 02:41 PM, Ville Syrjälä wrote:
> > On Mon, May 05, 2014 at 12:32:22PM -0700, Julius Werner wrote:
> >> Hmmm... very odd. I unfortunately don't have a machine that can easily
> >> do S4 at hand, but I did test this on an
On Wed, 7 May 2014, Thomas Petazzoni wrote:
> Commit 77dae54ab385033e488d8b07045bc7f8d931740f ('ARM: Kirkwood:
> ehci-orion: Add device tree binding') added the Device Tree binding
> for the ehci-orion driver. To achieve that with the irq, it used the
> irq_of_parse_and_map() function when probed
Dear Felipe Balbi,
On Wed, 7 May 2014 10:10:08 -0500, Felipe Balbi wrote:
> > ifneq ($(CONFIG_USB_XHCI_MVEBU), )
> > xhci-hcd-y += xhci-mvebu.o
> > endif
> >
> > Right?
>
> correct :-)
>
> > If so, then what about instead making CONFIG_USB_XHCI_MVEBU a bool
> > instead of a tristate? It's
On Wed, May 07, 2014 at 12:23:26PM +0200, Thomas Petazzoni wrote:
> Dear Felipe Balbi,
>
> On Tue, 6 May 2014 10:39:53 -0500, Felipe Balbi wrote:
>
> > > config USB_EHCI_HCD
> > > diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> > > index 7530468c9a4f..7a8db7f7dc01 100644
> >
Hello.
On 07-05-2014 3:00, dingu...@altera.com wrote:
From: Dinh Nguyen
The "dma-desc-enable" property can be used to enable descriptor DMA mode
for the DWC2 USB IP.
Signed-off-by: Dinh Nguyen
---
v2: Reword property description to enable instead of disable
---
Documentation/devicetre
Hello.
On 07-05-2014 7:50, Maxime Ripard wrote:
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
s/asserted/powered up/?
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard
---
On Wed, May 07, 2014 at 11:03:42AM -0400, Alan Stern wrote:
> On Wed, 7 May 2014, Zhuang Jin Can wrote:
>
> > A delayed status request may be queued before composite framework returns
> > USB_GADGET_DELAYED_STATUS, because the thread queueing the request can run
> > on a different core in parallel
On Thu, 8 May 2014, Zhuang Jin Can wrote:
> > A similar problem can occur in the opposite sense: The thread queuing
> > the delayed status request might be delayed for so long that another
> > SETUP packet arrives from the host first. In that case, the delayed
> > status request is a response for
Hi,
On Wed, May 07, 2014 at 05:45:32PM +0300, Mathias Nyman wrote:
> On 05/06/2014 11:43 PM, Felipe Balbi wrote:
> >Hi Mathias,
> >
> >I was using (up until today) v3.13 (on my desktop PC) to test LPM
> >transitions against OMAP5. Since I was having some issues with U1 exit
> >after some 200 itera
On Wed, 7 May 2014, Felipe Balbi wrote:
> > I think these patches could be related:
> >
> > commit 25cd2882e2fc8bd8ed7acaee0ec979f11feda6d7
> > usb/xhci: Change how we indicate a host supports Link PM.
> >
> > commit 140e3026a57ab7d830dab2f2c57796c222db0ea9
> > Revert "usbcore: set lpm_capable f
On Wed, May 07, 2014 at 01:37:29PM -0400, Alan Stern wrote:
> On Wed, 7 May 2014, Felipe Balbi wrote:
>
> > > I think these patches could be related:
> > >
> > > commit 25cd2882e2fc8bd8ed7acaee0ec979f11feda6d7
> > > usb/xhci: Change how we indicate a host supports Link PM.
> > >
> > > commit 140
From: Bjørn Mork
Date: Sat, 3 May 2014 16:12:47 +0200
> Fixes this warning introduced by commit 5b8f15f78e6f
> ("net: cdc_mbim: handle IPv6 Neigbor Solicitations"):
>
> ===
> [ INFO: suspicious RCU usage. ]
> 3.15.0-rc3 #213 Tainted: GW O
> -
Mike is not on the list and has problems with getting this device to work.
lsusb says:-
Bus 002 Device 005: ID 1d5c:2000 Fresco Logic Inc. USB3 USB to VGA adapter
It doesn't work with the udlfb module.
How can he gather relevant information from Windows that will help in
getting it supported u
As far as gr_queue() is called with spinlock held,
we have to pass GFP_ATOMIC regardless of gfp argument.
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Alexey Khoroshilov
---
drivers/usb/gadget/gr_udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
>
> I got it. There doesn't seem to be anything wrong with the data in the
> file. This means whatever the problem is, there's a good chance we
> can't find it through software.
>
> Does your computer have any USB-2 ports? Or is it possible to disable
> the USB-3 controllers in the BIOS? It wou
On Wed, May 07, 2014 at 07:05:30PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 07 May 2014 09:20 AM, Maxime Ripard wrote:
> > The USB phy controller in the A31 differs mostly from the older controllers
> > because it has a clock dedicated for each phy, while the older ones were
>
On Wed, May 07, 2014 at 08:26:39PM +0400, Sergei Shtylyov wrote:
> Hello.
>
> On 07-05-2014 7:50, Maxime Ripard wrote:
>
> >The OHCI controllers used in the Allwinner A31 are asserted in reset using a
>
>s/asserted/powered up/?
No. There's an external reset controller that maintains these d
On Wed, May 07, 2014 at 10:25:55AM -0400, Alan Stern wrote:
> On Tue, 6 May 2014, Maxime Ripard wrote:
>
> > From: Boris BREZILLON
> >
> > On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
> > be deasserted for the EHCI block to be usable.
> >
> > Add support for an opti
Hi,
(2014/05/07 22:52), Thomas Petazzoni wrote:
> diff --git a/drivers/usb/host/xhci-mvebu.h b/drivers/usb/host/xhci-mvebu.h
> new file mode 100644
> index 000..61d09b6
> --- /dev/null
> +++ b/drivers/usb/host/xhci-mvebu.h
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright (C) 2014 Marvell
> + *
> + * G
On Wed, May 07, 2014 at 12:59:06PM -0400, Alan Stern wrote:
> On Thu, 8 May 2014, Zhuang Jin Can wrote:
>
> > > A similar problem can occur in the opposite sense: The thread queuing
> > > the delayed status request might be delayed for so long that another
> > > SETUP packet arrives from the host
Changes since v8 [1]:
* Added patch 1 from Alan "USB: mutual exclusion for resetting a hub and
power-managing a port"
* Reworked patch 9 "usb: make usb_port flags atomic, rename
did_runtime_put to child_usage" to move the flags from struct usb_port
to struct usb_hub. Also clarified that did
Once usb-acpi has set the port's connect type the usb_device's
->removable attribute can be set in the standard location
set_usb_port_removable().
This also changes behavior in the case where the firmware says that the
port connect type is unknown. In that case just use the default setting
determ
From: Alan Stern
The USB core doesn't properly handle mutual exclusion between
resetting a hub and changing the power states of the hub's ports. We
need to avoid sending port-power requests to the hub while it is being
reset, because such requests cannot succeed.
This patch fixes the problem by
The current port name "portX" is ambiguous. Before adding more port
messages rename ports to "-portX"
This is an ABI change, but the suspicion is that it will go unnoticed as
the port power control implementation has been broken since its
introduction. If however, someone was relying on the old
In preparation for synchronizing port handling with pm_runtime
transitions refactor port handling into its own subroutine.
We expect that clearing some status flags will be required regardless of
the port state, so handle those first and group all non-trivial actions
at the bottom of the routine.
Three reasons:
1/ It's an invalid operation on usb3 ports
2/ There's no guarantee of when / if a usb2 port has entered an error
state relative to PORT_POWER request
3/ The port is active / powered at this point, so khubd will clear it as
a matter of course
Acked-by: Alan Stern
Signed-off-by
The port pm_runtime implementation unconditionally clears FEAT_C_ENABLE
after clearing PORT_POWER, but the bit is reserved on usb3 hub ports.
We expect khubd to be prevented from running because the port state is
not RPM_ACTIVE, so we need to clear any errors for usb2 ports.
Acked-by: Alan Stern
ACPI identifies peer ports by setting their 'group_token' and
'group_position' _PLD data to the same value. If a platform has tier
mismatch [1] , ACPI can override the default (USB3 defined) peer port
association for internal hubs. External hubs follow the default peer
association scheme.
Locati
Assume that the peer of a superspeed port is the port with the same id
on the shared_hcd root hub. This identification scheme is required of
external hubs by the USB3 spec [1]. However, for root hubs, tier mismatch
may be in effect [2]. Tier mismatch can only be enumerated via platform
firmware.
Given that root hub port peers are already established, external hub peer
ports can be determined by traversing the device topology:
1/ ascend to the parent hub and find the upstream port_dev
2/ walk ->peer to find the peer port
3/ descend to the peer hub via ->child
4/ find the port with the m
A hub indicates whether it supports per-port power control via the
wHubCharacteristics field in its descriptor. If it is not supported
a hub will still emulate ClearPortPower(PORT_POWER) requests by
stopping the link state machine. However, since this does not save
power do not bother suspending.
The usb topology after this change will have symlinks between usb3 ports
and their usb2 peers, for example:
usb2/2-1/2-1:1.0/2-1-port1/peer => ../../../../usb3/3-1/3-1:1.0/3-1-port1
usb2/2-1/2-1:1.0/2-1-port2/peer => ../../../../usb3/3-1/3-1:1.0/3-1-port2
usb2/2-1/2-1:1.0/2-1-port3/peer => ../../.
ClearPortFeature(PORT_POWER) on a usb3 port places the port in either a
DSPORT.Powered-off-detect / DSPORT.Powered-off-reset loop, or the
DSPORT.Powered-off state. There is no way to ensure that RX
terminations will persist in this state, so it is possible a device will
degrade to its usb2 connect
We want to manipulate ->did_runtime_put in usb_port_runtime_resume(),
but we don't want that to collide with other updates. Move usb_port
flags to new port-bitmap fields in usb_hub. "did_runtime_put" is renamed
"child_usage_bits" to reflect that it is strictly standing in for the
fact that usb_dev
Per Alan:
"You mean from within hub_handle_remote_wakeup()? That routine will
never get called if CONFIG_PM_RUNTIME isn't enabled, because khubd
never sees wakeup requests if they arise during system suspend.
In fact, that routine ought to go inside the "#ifdef CONFIG_PM_RUNTIME"
portion of hub.c
In general we do not want khubd to act on port status changes that are
the result of in progress resets or USB runtime PM operations.
Specifically port power control testing has been able to trigger an
unintended disconnect in hub_port_connect_change(), paraphrasing:
if ((portstatus & USB_
From: Lan Tianyu
describe the mechanisms for controlling port power policy and
discovering the port power state.
Cc: Oliver Neukum
[oliver]: fixes, clarification of wakeup vs port-power-control
Signed-off-by: Lan Tianyu
[sarah]: wordsmithing
[djbw]: updates for peer port changes
Signed-off-by:
If a port is powered-off, or in the process of being powered-off, prevent
khubd from operating on it. Otherwise, the following sequence of events
leading to an unintended disconnect may occur:
Events:
(0)
(1) hub 2-2:1.0: hub_resume
(2) hub 2-2:1.0: port 1: status 0301 change
(3) hub 2-2:1.
Resuming a powered down port sometimes results in the port state being
stuck in the training sequence.
hub 3-0:1.0: debounce: port 1: total 2000ms stable 0ms status 0x2e0
port1: can't get reconnection after setting port power on, status -110
hub 3-0:1.0: port 1 status .02e0 after resume, -
Unconditionally wake up the child device when the power session is
recovered.
This address the following scenarios:
1/ The device may need a reset on power-session loss, without this
change port power-on recovery exposes khubd to scenarios that
usb_port_resume() is set to handle. Prior to
Hi Sylwester,
On Tue, May 6, 2014 at 7:57 PM, Sylwester Nawrocki
wrote:
> On 28/04/14 08:17, Vivek Gautam wrote:
>> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
>> The new driver uses the generic PHY framework and will interact
>> with DWC3 controller present on Exynos5 series
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