On 04/30/2014 06:20 PM, Nishanth Menon wrote:
> On Tue, Apr 29, 2014 at 11:16 AM, Felipe Balbi wrote:
>> On Tue, Apr 29, 2014 at 11:14:20AM -0500, Felipe Balbi wrote:
>>> On Tue, Apr 29, 2014 at 10:50:39AM +0300, Roger Quadros wrote:
+Nishant
Hi,
On 04/28/2014 07:03 PM, Fe
> Hi
> I've done some initial hacking for the z27xx platforms USB detection and
> made at least the plug and play activities made detected by the USB host.
> But for some reason the ULPI interface doesn't seem to be reacting onto
> my commands I'm writing into its memory areas, so enumeration alw
Hi
> Just give some generic tips:
> - check if you can read pid and vip of this ulpi transceiver
I can read them, the are 0x0451 and 0x1508. So Vendor is Texas Instruments.
Can that be?!
> - If you can't, please check if the clock of ulpi is existed or
> not, it is an external clock, and check the
Hello,
W dniu 02.05.2014 17:24, Felipe Balbi pisze:
On Wed, Apr 30, 2014 at 09:36:01PM -0400, Michal Nazarewicz wrote:
On Thu, Apr 24 2014, Andrzej Pietrasiewicz wrote:
There is a custom (non-USB IF) extension to the USB standard:
This patch does not however implement responding to any
> > - check if you can read pid and vip of this ulpi transceiver
> I can read them, the are 0x0451 and 0x1508. So Vendor is Texas
> Instruments.
> Can that be?!
So, you have returned ulpi_init successfully?
> > - If you can't, please check if the clock of ulpi is existed or not,
> > it is an e
Hello,
W dniu 04.05.2014 12:31, Peter Stuge pisze:
Hi Peter,
Peter Chen wrote:
The step at the board:
root@freescale ~$ modprobe libcomposite
I guess this step is unneccessary, and that all neccessary modules
are loaded automatically on demand.
This one is necessary. The code which impl
Hi
> So, you have returned ulpi_init successfully?
Yes. I do. The ULPI init returns me a vendor and product ID.
> not check your code, it maybe a reset pin connect to ulpi phy.
> Alexander and Chris has run ulpi hardware successfully with chipidea
> driver, I have no ulpi hardware on hands.
Ok.
It
W dniu 04.05.2014 09:48, Peter Chen pisze:
Hi Sebastian & Andrzej,
My questions:
- How to choose gserial? I tried to remove the configuration
of mass storage, but both of configurations have been removed
root@freescale /sys/kernel/config/usb_gadget/g1$ rm -rf
configs/c.2/mass_storage
On 05/05/2014 10:23 AM, Roger Quadros wrote:
> On 04/30/2014 06:20 PM, Nishanth Menon wrote:
>> On Tue, Apr 29, 2014 at 11:16 AM, Felipe Balbi wrote:
>>> On Tue, Apr 29, 2014 at 11:14:20AM -0500, Felipe Balbi wrote:
On Tue, Apr 29, 2014 at 10:50:39AM +0300, Roger Quadros wrote:
> +Nishant
As clocks might be named differently on multiple platforms, use a generic
name in the driver and allow device tree node to specify the platform
specific clock name.
Signed-off-by: Roger Quadros
---
drivers/phy/phy-omap-usb2.c | 30 +++---
1 file changed, 23 insertions(+),
Hi,
This series enables the 2 USB ports on the DRA7-evm.
NOTE: USB1 port is hard coded to work in peripheral mode and USB2 port
in host mode. This is due to missing ID pin interrupt in pre ver.E boards.
USB1 port doesn't in peripheral mode out of the box due to missing VBUS
detection
and mailbo
This clock gate description is missing in the older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.
Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL
Use l3init_960m_gfclk as parent of u
Add "wkupclk" and "refclk" information to DT binding information.
Reviewed-by: Felipe Balbi
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentat
Add USB pinmux information and USB modes
for the USB controllers.
CC: Benoît Cousson
Reviewed-by: Felipe Balbi
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm
The USB2 PHY driver expects named clocks for wakeup clock
and reference clock. Provide this information for USB2 PHY
nodes in OMAP4 and OMAP5 SoC DTS.
CC: Benoît Cousson
Reviewed-by: Felipe Balbi
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/omap4.dtsi | 2 ++
arch/arm/boot/dts/omap5.dtsi
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
CC: Benoît Cousson
Reviewed-by: Felipe Balbi
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7.dtsi
Add the sysconfig class bits for the Super Speed USB
controllers
CC: Paul Walmsley
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_h
Hi Michal,
W dniu 01.05.2014 03:42, Michal Nazarewicz pisze:
On Thu, Apr 24 2014, Andrzej Pietrasiewicz wrote:
@@ -438,8 +440,46 @@ static int config_desc(struct usb_composite_dev *cdev,
unsigned w_value)
}
- /* This is a lookup by config *INDEX* */
w_value &= 0xff;
+
To use auto U0-U1/U2 transition by xhci platform device add
(en/dis)able_usb3_lpm_timeout function to the xhci_plat_xhci_driver struct.
Signed-off-by: Pratyush Anand
Tested-by: Aymen Bouattay
---
drivers/usb/host/xhci-plat.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/hos
These patches provides support of LPM capability to the dwc3 xhci hosts.
Patches have been tested on STih407.
Changes since V1:
-- patches have been rebased on next branch of balbi/usb.git.
-- Minor comment of Mathias for V1 have been incorporated.
-- New rebased patches h
As best case, a host controller should support U0 to U1 switching for
the devices connected below any tier of hub level supported by usb
specification. Therefore xhci_check_tier_policy should always return
success as default implementation.
A host should be able to issue LGO_Ux after the timeout c
When a USB device is disconnected, usb_unbind_interface is called, which
tries to enable and disable LPM. usb_enable_lpm also try to send a
control command SET SEL to the device.
Since device is already disconnected, therefore it does not make sense
to execute usb_(en/dis)able_lpm.
This patch retur
If an xhci platform supports USB3 LPM capability then enable
XHCI_LPM_SUPPORT quirk flag.
Signed-off-by: Pratyush Anand
---
Documentation/devicetree/bindings/usb/usb-xhci.txt | 2 ++
drivers/usb/host/xhci-plat.c | 6 +
include/linux/usb/xhci_pdriver.h
All dwc3 based xhci host controller supports USB3.0 LPM functionality.
Therefore enable it in platform data for all dwc3 based xhci device.
Signed-off-by: Pratyush Anand
---
drivers/usb/dwc3/host.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/host.c b/drivers/
W dniu 01.05.2014 03:48, Michal Nazarewicz pisze:
On Thu, Apr 24 2014, Andrzej Pietrasiewicz wrote:
In order for usb functions to expose OS descriptors they
need to be made aware of OS descriptors. This involves
extending the "options" structure and setting up
appropriate associations.
Signed-o
Two simple test cases for interrupt endpoints are added to the usbtest.c file.
These are simple non-queued interrupt IN and interrupt OUT transfers. Currently,
only gadget zero is capable of executing the interrupt EP test cases. However,
extending the same to other gadgets is extremely simple and
This patchset adds support for interrupt EP and the corresponding test cases to
gadget zero. The code has been rebased and tested on Kernel v3.15-rc3
V1 -> V2
- Modified the alternate interface from having 6 EPs (2 - Interrupt, 2 Bulk, 2
Isoc) to 2 EPs (Interrupt only)
RFC -> V1
- Added supp
Interrupt endpoints behave quite similar to the bulk endpoints with the
difference that the endpoints expect data sending/reception request at
particular intervals till the whole data has not been transmitted.
The interrupt EP support is added to gadget zero. A new alternate setting (=2)
has been
W dniu 01.05.2014 03:36, Michal Nazarewicz pisze:
On Thu, Apr 24 2014, Andrzej Pietrasiewicz wrote:
There is a custom (non-USB IF) extension to the USB standard:
http://msdn.microsoft.com/library/windows/hardware/gg463182
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/co
The exynos5250-snow has a SMSC USB3503 connected in
hardware only mode like a PHY. Enable support for it,
and add necessary 'reset-gpio' for it.
This is in correspondance to similar patch by Mark Brown
7c1b0ec ARM: dts: Enable USB hub on Arndale
Signed-off-by: Vivek Gautam
---
Based on 'for-nex
The exynos5420-peach-pit has a SMSC USB3503 connected in
hardware only mode like a PHY. Enable support for it,
and add necessary 'reset-gpio' for it.
This is in correspondance to similar patch by Mark Brown
7c1b0ec ARM: dts: Enable USB hub on Arndale
Signed-off-by: Vivek Gautam
---
Based on 'fo
Hi Felipe
W dniu 24.04.2014 11:17, Andrzej Pietrasiewicz pisze:
Example of using OS Descriptors in a legacy gadget.
Signed-off-by: Andrzej Pietrasiewicz
---
drivers/usb/gadget/ether.c | 58 ++
1 file changed, 53 insertions(+), 5 deletions(-)
Th
On Sat, May 03, 2014 at 09:56:32AM +0300, Ivan T. Ivanov wrote:
> On Wed, 2014-04-30 at 11:38 -0500, Felipe Balbi wrote:
> > this solves the following build warning found when
> > running compile tests.
> >
> > drivers/usb/phy/phy-msm-usb.c: In function ‘msm_otg_read_dt’:
> > drivers/usb/phy/phy-m
On Mon, 2014-05-05 at 11:07 +0530, Suresh Kumar N. wrote:
> Hi,
>
> I am new to udev and device enumeration.
>
> I am interested to know how USB Data Card would get enumerated.
>
> Based on my understanding Data Card can get enumerated below 2 possible ways -
> 1. As a modem
> 2. As a Networ
On Mon, May 05, 2014 at 10:03:31AM -0500, Felipe Balbi wrote:
> On Sat, May 03, 2014 at 09:56:32AM +0300, Ivan T. Ivanov wrote:
> > On Wed, 2014-04-30 at 11:38 -0500, Felipe Balbi wrote:
> > > this solves the following build warning found when
> > > running compile tests.
> > >
> > > drivers/usb/p
On Mon, May 05, 2014 at 03:30:08PM +0530, Pratyush Anand wrote:
> All dwc3 based xhci host controller supports USB3.0 LPM functionality.
> Therefore enable it in platform data for all dwc3 based xhci device.
>
> Signed-off-by: Pratyush Anand
> ---
> drivers/usb/dwc3/host.c | 10 ++
> 1 f
On Mon, May 05, 2014 at 08:03:04PM +0530, George Cherian wrote:
> Remove the dsps_debugfs entry as part of musb_platform_exit().
> Without this MUSB never gets probed if compiled built-in.
>
> Signed-off-by: George Cherian
> ---
> drivers/usb/musb/musb_dsps.c | 1 +
> 1 file changed, 1 insertion
On Fri, May 02, 2014 at 09:48:02PM -0500, Felipe Balbi wrote:
[snip]
> if original driver is GPL, how about sending it for inclusion in
> mainline ? If anybody wants to sponsor one USB3380 for my testing, I'd
> be very thankful too as that'll help me make sure things get tested
> before going ups
On Mon, May 05, 2014 at 10:07:21AM -0700, Greg Kroah-Hartman wrote:
> On Mon, May 05, 2014 at 08:45:37AM +0200, Andrzej Pietrasiewicz wrote:
> > Hi Felipe,
> >
> > W dniu 30.04.2014 18:24, Felipe Balbi pisze:
> > >On Thu, Apr 24, 2014 at 11:17:11AM +0200, Andrzej Pietrasiewicz wrote:
> > >>There i
On Mon, May 05, 2014 at 08:45:37AM +0200, Andrzej Pietrasiewicz wrote:
> Hi Felipe,
>
> W dniu 30.04.2014 18:24, Felipe Balbi pisze:
> >On Thu, Apr 24, 2014 at 11:17:11AM +0200, Andrzej Pietrasiewicz wrote:
> >>There is a custom (non-USB IF) extension to the USB standard:
> >>
> >>http://msdn.micr
On Mon, May 05, 2014 at 12:54:40PM +0300, Roger Quadros wrote:
> As clocks might be named differently on multiple platforms, use a generic
> name in the driver and allow device tree node to specify the platform
> specific clock name.
>
> Signed-off-by: Roger Quadros
Reviewed-by: Felipe Balbi
>
On Mon, May 05 2014, Andrzej Pietrasiewicz wrote:
> Do I get it right that you suggest creating a struct and then
> memcpy'ing it to the destination buffer?
>
> Something on the lines of:
>
> struct usb_os_string {
> __u8bLength;
> __u8bDescriptorType;
> __u8qwSignatur
On Sun, 4 May 2014, Russel Hughes wrote:
> > The audio data is contained in the lines that have a 'Z'. Just search
> > for the first such line and then go back twenty or so lines before that
> > to provide some context.
> >
> > Alan Stern
>
> This OK?
Yep, that's what I wanted. However, this s
On Mon, May 05 2014, Andrzej Pietrasiewicz wrote:
> When a gadget is composed with configfs the usb_add_config() is invoked
> each time a configuration's directory is created, so this way configurations'
> indices are determined. If we were to rearrange the configurations if
> one of them becomes "
From: Bjørn Mork
Date: Fri, 2 May 2014 23:27:00 +0200
> Commit 4d619f625a60 ("net: cdc_ncm: no point in filling up the NTBs
> if we send ZLPs") changed the padding logic for devices with the ZLP
> flag set. This meant that frames of any size will be sent without
> additional padding, except for
On Mon, May 05, 2014 at 01:34:10PM +0530, Amit Virdi wrote:
> [Re-sending, as previously it was HTML formatted and rejected by the server]
>
> Dear Felipe,
>
> On Fri, Feb 28, 2014 at 1:19 AM, Felipe Balbi wrote:
> >
> > by setting IOC always, we can recycle TRBs a
> > lot sooner at the expense
Hmmm... very odd. I unfortunately don't have a machine that can easily
do S4 at hand, but I did test this on an IVB with XHCI_RESET_ON_RESUME
in S3 (essentially the same code path), and I didn't run into any
problems.
How exactly does your machine fail on resume? Is it a kernel crash or
just a han
The following changes since commit d1db0eea852497762cab43b905b879dfcd3b8987:
Linux 3.15-rc3 (2014-04-27 19:29:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/
tags/usb-3.15-rc4
for you to fetch changes up to 6ed07d45d09bc2aa60e
From: Dinh Nguyen
The "dma-desc-enable" property can be used to disable descriptor DMA mode
for the DWC2 USB IP.
Signed-off-by: Dinh Nguyen
---
Documentation/devicetree/bindings/usb/dwc2.txt |5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.
From: Dinh Nguyen
Even though the IP supports Descriptor DMA mode, it does not support SPLIT
transactions in this mode. Since the driver can get the Descriptor DMA mode
support from hardware, the driver in its currently form cannot fully support
LS/FS devices connected to a HS Hub when Descriptor
This commit allows to use the PHY provided through the device tree. It
will be useful for the Armada 375 SoCs. if no PHY is provided then the
behavior of the driver is unchanged.
Signed-off-by: Gregory CLEMENT
---
drivers/usb/host/ehci-orion.c | 25 +++--
1 file changed, 23 i
Extend the compatible string list with armada-375-xhci. It is used to
describe xHCI controller which is in the Armada 375 SoC.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation
This patch add the selection of the config symbol to build the USB3
support for Armada 375.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 7960f218702b..95afc7677ee
The Marvell Armada 375 SoCs contain a xHCI host. This commit adds the
Device Tree description of this interfaces at the SoC level, and also
enables the USB3 port on the Armada 375 DB platform.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-375-db.dts | 4
arch/arm/boot/dts/arm
The Marvell Armada 375 SoCs contains one EHCI host. This commit adds
the Device Tree description of this interfaces at the SoC level, and
also enables the USB2 port on the Armada 375 DB platform.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-375-db.dts | 4
arch/arm/boot/dts/
On Armada 375, the USB cluster allows to control the cluster composed
of the USB2 and USB3 host controllers.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-375.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/armada-375.dtsi
b/arch/arm/boot/dts/armad
The Armada 375 SoC comes with an USB2 host and device controller and
an USB3 controller. The USB cluster control register allows to manage
common features of both USB controllers. It uses the generic PHY
framework
Signed-off-by: Gregory CLEMENT
---
drivers/phy/Kconfig | 5 ++
driv
Armada 375 comes with an USB2 host and device controller and an USB3
controller. The USB cluster control register allows to manage common
features of both USB controllers.
Signed-off-by: Gregory CLEMENT
---
.../bindings/phy/armada-375-usb-phy-cluster.txt | 19 +++
1 file ch
The Marvell Armada 38x platform needs the xhci_mvebu driver enabled
for the xHCI USB hosts, so this commit enables the corresponding
Kconfig option in mvebu_v7_defconfig.
Signed-off-by: Gregory CLEMENT
---
arch/arm/configs/mvebu_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/ar
The Marvell Armada 38x platform needs the xhci_mvebu driver enabled
for the xHCI USB hosts, so this commit enables the corresponding
Kconfig option in multi_v7_defconfig.
Signed-off-by: Gregory CLEMENT
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/ar
The Marvell Armada 38x SoCs contains one EHCI host. This commit adds
the Device Tree description of this interface at the SoC level, and
also enables the USB2 port on the Armada 385 DB platform.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-385-db.dts | 4
arch/arm/boot/dts/ar
For the Armada 375 SoC which comes with an xhci controller. Currently
the quirk is the same that the Armada 380/385 one, but by introducing
a new compatible string it will allow to make the driver evolve
seamless.
Signed-off-by: Gregory CLEMENT
---
drivers/usb/host/xhci-plat.c | 5 +
1 file
This patch add the selection of the config symbol to build the USB3
support for Armada 38x.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 3f73eecbcfb0..7960f218702
Extend the compatible string list with armada-380-xhci. It is used to
describe xhci controller which is in the Armada 38x SoCs.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentatio
The Marvell Armada 38x SoCs contains two xHCI host. This commit adds
the Device Tree description of those interfaces at the SoC level, and
also enables the two USB3 ports on the Armada 385 DB platform and one
USB3 port on the Armada 385 RD platform.
Signed-off-by: Gregory CLEMENT
---
arch/arm/bo
For the Armada 38x SoCs which come with an xhci controller, specific
initialization must be done during probe related to the MBus windows
configuration. This patch adds the support of this quirk.
Signed-off-by: Gregory CLEMENT
---
drivers/usb/host/Kconfig | 7 +
drivers/usb/host/Makefi
Some platform (such as the Armada 38x ones) can gate the clock of
their USB controller. This patch add the support for the clock, by
enabling them during probe and disabling them on remove.
As not all platforms have clock support then enabling and disabling
the clocks have been placed in separate
Sorting the headers in alphabetic order will help to reduce the conflict
when adding new headers later.
Signed-off-by: Gregory CLEMENT
Acked-by: Felipe Balbi
---
drivers/usb/host/xhci-plat.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/xhci-plat.c b
This patch adds an xhci->priv field for private use by xHCI platform
drivers. This field was present for OHCI and EHCI and it was not
needed until now for xHCI. With the introduction of the clock support,
then a private field will be useful, so let's mimic what have been
done for the other HCI.
Si
This patch set adds the USB support for the Armada 38x Armada
375. These SoCs use an xHCI but still need specific initialization,
mainly to setup the windows memory on the mbus. They also use the same
controller that the other mvebu SoC for EHCI.
Since the 2nd version I converted the usb cluster d
In order to disable the clock while the module was removing, a call to
devm_clk_get() was made. This was wrong and lead to a leak module
ref-counts.
In order to have a reference of the clock get, a private structure was
added using the override mechanism provided by the ehci framework.
The bug wa
>
> On Wed, 30 Apr 2014, Felipe Balbi wrote:
>
> > > > Now say you want to use that gadget driver which is deferred, you
> > > > unload first gadget driver and then nothing happens because you
> > > > have no way to tell that gadget driver that you want it to bind to
> > > > the UDC which is no
On Mon, May 05, 2014 at 11:09:30AM +0200, Andrzej Pietrasiewicz wrote:
> W dniu 04.05.2014 09:48, Peter Chen pisze:
> >Hi Sebastian & Andrzej,
>
>
>
> >
> >My questions:
> >
>
>
>
> >- How to choose gserial? I tried to remove the configuration
> >of mass storage, but both of configurations ha
On Tue, May 06, 2014 at 02:14:00AM +0200, Gregory CLEMENT wrote:
> @@ -118,7 +158,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
>
> hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
> if (!hcd)
> - return -ENOMEM;
> + ret = -ENOMEM
On Mon, May 05, 2014 at 11:35:57PM +0800, Felipe Balbi wrote:
> On Mon, May 05, 2014 at 03:30:08PM +0530, Pratyush Anand wrote:
> > All dwc3 based xhci host controller supports USB3.0 LPM functionality.
> > Therefore enable it in platform data for all dwc3 based xhci device.
> >
> > Signed-off-by:
To use auto U0-U1/U2 transition by xhci platform device add
(en/dis)able_usb3_lpm_timeout function to the xhci_plat_xhci_driver struct.
Signed-off-by: Pratyush Anand
Tested-by: Aymen Bouattay
---
drivers/usb/host/xhci-plat.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/hos
If an xhci platform supports USB3 LPM capability then enable
XHCI_LPM_SUPPORT quirk flag.
Signed-off-by: Pratyush Anand
---
Documentation/devicetree/bindings/usb/usb-xhci.txt | 2 ++
drivers/usb/host/xhci-plat.c | 6 +
include/linux/usb/xhci_pdriver.h
When a USB device is disconnected, usb_unbind_interface is called, which
tries to enable and disable LPM. usb_enable_lpm also try to send a
control command SET SEL to the device.
Since device is already disconnected, therefore it does not make sense
to execute usb_(en/dis)able_lpm.
This patch retur
All dwc3 based xhci host controller supports USB3.0 LPM functionality.
Therefore enable it in platform data for all dwc3 based xhci device.
Signed-off-by: Pratyush Anand
---
drivers/usb/dwc3/host.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/usb/dwc3/host.c b/driver
As best case, a host controller should support U0 to U1 switching for
the devices connected below any tier of hub level supported by usb
specification. Therefore xhci_check_tier_policy should always return
success as default implementation.
A host should be able to issue LGO_Ux after the timeout c
These patches provide support of LPM capability to the dwc3 xhci hosts.
Patches have been tested on STih407.
Changes since V2:
-- checkpatch warning removed.
-- xhci pdata initialized with zero using memset.
Changes since V1:
-- patches have been rebased on next branch of
On 5/6/2014 12:56 AM, Felipe Balbi wrote:
I understand that enabling XferInProgress event for bulk/interrupt
>transfers will completely
>change the design of the dwc3 driver and hence is not the viable solution
>to the issue here.
just send a patch enabling XferInProgress.. I haven't gotten to i
Hi Peter,
W dniu 06.05.2014 03:01, Peter Chen pisze:
On Mon, May 05, 2014 at 11:09:30AM +0200, Andrzej Pietrasiewicz wrote:
W dniu 04.05.2014 09:48, Peter Chen pisze:
Hi Sebastian & Andrzej,
1. I have setup successfully for running mass storage and CDC ACM at the
same time with below ste
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