Re: [PATCH] phy: exynos5-drd: Fix PHYPARAM1_PCS_TXDEEMPH definition

2014-09-21 Thread Vivek Gautam
On Mon, Sep 22, 2014 at 7:06 AM, Anton Tikhomirov wrote: > According to user manual, pcs_tx_deemph_3p5db field in PHYPARAM1 > register is 6bits wide, so mask value should be 0x3f instead > of 0x1f. Additionally, this patch renames the macro to correctly > reflect the field name which we see in SoC

Re: [PATCH] phy: exynos5-drd: Fix PHYPARAM1_PCS_TXDEEMPH definition

2014-09-21 Thread Jingoo Han
On Monday, September 22, 2014 10:37 AM, Anton Tikhomirov wrote: > > According to user manual, pcs_tx_deemph_3p5db field in PHYPARAM1 > register is 6bits wide, so mask value should be 0x3f instead > of 0x1f. Additionally, this patch renames the macro to correctly > reflect the field name which we s