Hi Arnd,
2018-04-04 17:43 GMT+09:00 Arnd Bergmann :
> On Wed, Apr 4, 2018 at 10:00 AM, Felipe Balbi
> wrote:
>>
>> Hi,
>>
>> Masahiro Yamada writes:
> Each DWC3 instance is connected with
> multiple HS PHYs and multiple SS PHYs,
> depending on the number of ports.
in that c
On Wed, Apr 4, 2018 at 10:00 AM, Felipe Balbi
wrote:
>
> Hi,
>
> Masahiro Yamada writes:
Each DWC3 instance is connected with
multiple HS PHYs and multiple SS PHYs,
depending on the number of ports.
>>>
>>> in that case, you shouldn't need dwc3 at all. A Host-only dwc3 is xHCI
>>>
Hi,
Masahiro Yamada writes:
>>> Each DWC3 instance is connected with
>>> multiple HS PHYs and multiple SS PHYs,
>>> depending on the number of ports.
>>
>> in that case, you shouldn't need dwc3 at all. A Host-only dwc3 is xHCI
>> compliant. If you really don't have the gadget block, there's no n
2018-04-04 15:04 GMT+09:00 Felipe Balbi :
>
> Hi,
>
> Masahiro Yamada writes:
>> 2018-04-04 14:36 GMT+09:00 Felipe Balbi :
>>>
>>> Hi,
>>>
>>> Masahiro Yamada writes:
Currently, DWC3 core IP (drivers/usb/dwc3/core.c)
can take only one PHY phandle for each of SS, HS.
(phy-names DT p
Hi,
Masahiro Yamada writes:
> 2018-04-04 14:36 GMT+09:00 Felipe Balbi :
>>
>> Hi,
>>
>> Masahiro Yamada writes:
>>> Currently, DWC3 core IP (drivers/usb/dwc3/core.c)
>>> can take only one PHY phandle for each of SS, HS.
>>> (phy-names DT property is "usb2-phy" and "usb3-phy" for each)
>>
>> We
2018-04-04 14:36 GMT+09:00 Felipe Balbi :
>
> Hi,
>
> Masahiro Yamada writes:
>> Currently, DWC3 core IP (drivers/usb/dwc3/core.c)
>> can take only one PHY phandle for each of SS, HS.
>> (phy-names DT property is "usb2-phy" and "usb3-phy" for each)
>
> We never had any other requirements :-)
>
>>
Hi,
Masahiro Yamada writes:
> Currently, DWC3 core IP (drivers/usb/dwc3/core.c)
> can take only one PHY phandle for each of SS, HS.
> (phy-names DT property is "usb2-phy" and "usb3-phy" for each)
We never had any other requirements :-)
> The DWC3 core IP is provided by Synopsys,
> but some SoC
Hi.
Currently, DWC3 core IP (drivers/usb/dwc3/core.c)
can take only one PHY phandle for each of SS, HS.
(phy-names DT property is "usb2-phy" and "usb3-phy" for each)
The DWC3 core IP is provided by Synopsys,
but some SoC-dependent parts (a.k.a glue-layer)
are implemented by SoC venders.
The num
