Hi Mike,
On 27/11/2013 22:48, Mike Turquette wrote:
Quoting Boris BREZILLON (2013-11-12 13:57:19)
+static const struct clk_ops pll_ops = {
+ .prepare = clk_pll_prepare,
+ .is_prepared = clk_pll_is_ready,
+ .disable = clk_pll_disable,
+ .is_enabled = clk_pll_is_ready,
+
Quoting Boris BREZILLON (2013-11-12 13:57:19)
> +static const struct clk_ops pll_ops = {
> + .prepare = clk_pll_prepare,
> + .is_prepared = clk_pll_is_ready,
> + .disable = clk_pll_disable,
> + .is_enabled = clk_pll_is_ready,
> + .recalc_rate = clk_pll_recalc_rate,
> +
This patch adds new at91 pll clock implementation using common clk framework.
The pll clock layout describe the PLLX register layout.
There are four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3
PLL clocks are given characteristics:
- min/max clock source rate
- ranges of
