Hi,
Janusz Dziedzic writes:
>> John Youn writes:
+ dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
+
>> After that evt->buf[lpos, lpos + count] seems goes back to HW, so
>> thread should not rely on this?
>>
>> Or I miss something?
>
> Hi,
On 9 November 2016 at 09:05, Felipe Balbi wrote:
>
> Hi,
>
> John Youn writes:
>>> + dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
>>> +
> After that evt->buf[lpos, lpos + count] seems goes back to HW, so
> thread should not rely on this?
>
> Or I miss something
Hi,
John Youn writes:
>> + dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
>> +
After that evt->buf[lpos, lpos + count] seems goes back to HW, so
thread should not rely on this?
Or I miss something?
>>>
>>> Hi,
>>>
>>> Yes, you're right. That's a possibility
On 11/8/2016 6:09 AM, Felipe Balbi wrote:
>
> Hi,
>
> John Youn writes:
>> On 11/4/2016 2:13 AM, Janusz Dziedzic wrote:
>>> On 4 November 2016 at 07:41, Janusz Dziedzic
>>> wrote:
On 4 November 2016 at 02:31, John Youn wrote:
>
> Since we are saving the event count and handling t
Hi,
John Youn writes:
> On 11/4/2016 2:13 AM, Janusz Dziedzic wrote:
>> On 4 November 2016 at 07:41, Janusz Dziedzic
>> wrote:
>>> On 4 November 2016 at 02:31, John Youn wrote:
Since we are saving the event count and handling the events in the
threaded interrupt handler, we can
On 11/4/2016 2:13 AM, Janusz Dziedzic wrote:
> On 4 November 2016 at 07:41, Janusz Dziedzic
> wrote:
>> On 4 November 2016 at 02:31, John Youn wrote:
>>>
>>> Since we are saving the event count and handling the events in the
>>> threaded interrupt handler, we can write and clear out the eventcou
On 4 November 2016 at 07:41, Janusz Dziedzic wrote:
> On 4 November 2016 at 02:31, John Youn wrote:
>>
>> Since we are saving the event count and handling the events in the
>> threaded interrupt handler, we can write and clear out the eventcount in
>> the hard interrupt handler itself.
>>
>> This
On 4 November 2016 at 02:31, John Youn wrote:
>
> Since we are saving the event count and handling the events in the
> threaded interrupt handler, we can write and clear out the eventcount in
> the hard interrupt handler itself.
>
> This behavior will be required for IP 3.00a cores that need to us
Since we are saving the event count and handling the events in the
threaded interrupt handler, we can write and clear out the eventcount in
the hard interrupt handler itself.
This behavior will be required for IP 3.00a cores that need to use
interrupt moderation as a workaround for an RTL issue we
