Hi,
On Mon, Oct 20, 2014 at 11:38:23PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 10:10:26AM -0500, Felipe Balbi wrote:
> > Hi,
> >
> > On Fri, Oct 17, 2014 at 04:53:25PM +0800, Huang Rui wrote:
> > > The series of patches add AMD NL SoC support for DesignWare USB3 OTG
> > > IP with PCI bu
On Fri, Oct 17, 2014 at 10:10:26AM -0500, Felipe Balbi wrote:
> Hi,
>
> On Fri, Oct 17, 2014 at 04:53:25PM +0800, Huang Rui wrote:
> > The series of patches add AMD NL SoC support for DesignWare USB3 OTG
> > IP with PCI bus glue layer. This controller supported hibernation, LPM
> > erratum and use
Hi,
On Fri, Oct 17, 2014 at 04:53:25PM +0800, Huang Rui wrote:
> The series of patches add AMD NL SoC support for DesignWare USB3 OTG
> IP with PCI bus glue layer. This controller supported hibernation, LPM
> erratum and used the 2.80a IP version and amd own phy. Current
> implementation support b
Hi,
The series of patches add AMD NL SoC support for DesignWare USB3 OTG IP with
PCI bus glue layer. This controller supported hibernation, LPM erratum and used
the 2.80a IP version and amd own phy. Current implementation support both
simulation and SoC platform. And already tested with gadget zer
