Hi Felipe
On Friday, July 26, 2019 11:30 Ran Wang wrote:
>
> Hi Felipe,
>
> On Friday, July 26, 2019 05:56, Rob Herring wrote:
> >
> > On Wed, Jul 24, 2019 at 8:29 PM Ran Wang wrote:
> > >
> > > Hi Rob,
> > >
> > > On Thursday, July 25, 2019 04:42 Rob Herring wrote:
> > > >
> > > > On Fri, Ju
Hi Felipe,
On Friday, July 26, 2019 05:56, Rob Herring wrote:
>
> On Wed, Jul 24, 2019 at 8:29 PM Ran Wang wrote:
> >
> > Hi Rob,
> >
> > On Thursday, July 25, 2019 04:42 Rob Herring wrote:
> > >
> > > On Fri, Jul 12, 2019 at 02:42:05PM +0800, Ran Wang wrote:
> > > > Some Layerscape paltforms
On Wed, Jul 24, 2019 at 8:29 PM Ran Wang wrote:
>
> Hi Rob,
>
> On Thursday, July 25, 2019 04:42 Rob Herring wrote:
> >
> > On Fri, Jul 12, 2019 at 02:42:05PM +0800, Ran Wang wrote:
> > > Some Layerscape paltforms (such as LS1088A, LS2088A, etc) encounter
> > > USB detect failues when adding dma-
Hi Rob,
On Thursday, July 25, 2019 04:42 Rob Herring wrote:
>
> On Fri, Jul 12, 2019 at 02:42:05PM +0800, Ran Wang wrote:
> > Some Layerscape paltforms (such as LS1088A, LS2088A, etc) encounter
> > USB detect failues when adding dma-coherent to DWC3 node. This is
> > because the HW default cache
On Fri, Jul 12, 2019 at 02:42:05PM +0800, Ran Wang wrote:
> Some Layerscape paltforms (such as LS1088A, LS2088A, etc) encounter USB
> detect failues when adding dma-coherent to DWC3 node. This is because the
> HW default cache type configuration of those SoC are not right, need to
> be updated in D
Some Layerscape paltforms (such as LS1088A, LS2088A, etc) encounter USB
detect failues when adding dma-coherent to DWC3 node. This is because the
HW default cache type configuration of those SoC are not right, need to
be updated in DTS.
Signed-off-by: Ran Wang
---
Change in v2:
- New file
