, Mathias; linux-usb@vger.kernel.org; ejcar...@chromium.org
Subject: Re: [PATCH] xhci: Workaround to get D3 working in Intel xHCI
On Mon, Jul 13, 2015 at 4:03 PM, Mani, Rajmohan wrote:
> I implemented the original patch exactly the way you mentioned that would i)
> use a new quirk ii)
On Mon, Jul 13, 2015 at 4:03 PM, Mani, Rajmohan wrote:
> I implemented the original patch exactly the way you mentioned that would i)
> use a new quirk ii) do the vendor / device check within xhci_pci_quirks() and
> iii) do this in a separate function. When I sent this out internally to
> Mathi
: Workaround to get D3 working in Intel xHCI
Thanks Rajmohan. Comments inline.
On Thu, Jul 9, 2015 at 6:17 PM, wrote:
> From: Rajmohan Mani
>
> The xHCI in Intel CherryView / Braswell Platform requires a driver
> workaround to get xHCI D3 working. Without this workaround, xHCI might
Thanks Rajmohan. Comments inline.
On Thu, Jul 9, 2015 at 6:17 PM, wrote:
> From: Rajmohan Mani
>
> The xHCI in Intel CherryView / Braswell Platform requires
> a driver workaround to get xHCI D3 working. Without this
> workaround, xHCI might not enter D3.
>
> Workaround is to configure SSIC PORT
From: Rajmohan Mani
The xHCI in Intel CherryView / Braswell Platform requires
a driver workaround to get xHCI D3 working. Without this
workaround, xHCI might not enter D3.
Workaround is to configure SSIC PORT as "unused" before D3
entry and "used" after D3 exit. This is done through a
vendor spe
