Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-07-09 Thread Roger Quadros
On 07/08/2013 05:33 PM, Ruchika Kharwar wrote: > > On 07/08/2013 02:28 AM, Felipe Balbi wrote: >> On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote: >>> Addition of the M and N recommended values for the USB3 PHY DPLL. >>> Sysclk for DRA7xx is 20MHz. >>> This yields: >>> Clk = 20MHz

Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-07-08 Thread Ruchika Kharwar
On 07/08/2013 02:28 AM, Felipe Balbi wrote: On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote: Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Nikhil De

Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-07-08 Thread Felipe Balbi
On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote: > Addition of the M and N recommended values for the USB3 PHY DPLL. > Sysclk for DRA7xx is 20MHz. > This yields: > Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz > > Signed-off-by: Nikhil Devshatwar > Signed-off-by: Ruchika K

[PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-06-21 Thread Ruchika Kharwar
Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Nikhil Devshatwar Signed-off-by: Ruchika Kharwar --- drivers/usb/phy/phy-omap-usb3.c |7 ++- 1 file changed, 6

Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-06-21 Thread George Cherian
On 5/31/2013 1:24 AM, Ruchika Kharwar wrote: Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Ruchika Kharwar --- drivers/usb/phy/phy-omap-usb3.c |7 ++- 1 f

[PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-05-30 Thread Ruchika Kharwar
Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Ruchika Kharwar --- drivers/usb/phy/phy-omap-usb3.c |7 ++- 1 files changed, 6 insertions(+), 1 deletions(-) di