On Mon, Sep 02, 2019 at 11:54:45AM +0800, JC Kuo wrote:
> Tegra194 XUSB host controller has rearranged mailbox registers. This
> commit makes mailbox registers address a part of "soc" data so that
> xhci-tegra driver can be used for Tegra194.
>
> Signed-off-by: JC Kuo
> ---
> drivers/usb/host/xh
r
>
> Signed-off-by: Nagarjuna Kristam
> Acked-by: Thierry Reding
> ---
> drivers/usb/gadget/udc/Kconfig | 11 +
> drivers/usb/gadget/udc/Makefile |1 +
> drivers/usb/gadget/udc/tegra_xudc.c | 3808
> +++
> 3 files changed, 3820
On Thu, Aug 08, 2019 at 03:07:18PM +0530, Nagarjuna Kristam wrote:
> This is the sixth version of series "Tegra XUSB gadget driver support"
>
> Patches 1-3 are phy driver changes to add support for device
> mode.
> Patches 4-7 are changes related to XUSB device mode
> controller driver.
> Patch 8
sb-tegra210.c | 57
> +++
> drivers/phy/tegra/xusb.c | 22 +++
> drivers/phy/tegra/xusb.h | 2 ++
> include/linux/phy/tegra/xusb.h| 4 ++-
> 4 files changed, 84 insertions(+), 1 deletion(-)
Looks good to me now:
Acked-by: Thierry Reding
eviewed-by: JC Kuo
> ---
> .../devicetree/bindings/usb/nvidia,tegra-xudc.txt | 110
> +
> 1 file changed, 110 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt
Acked-by: Thierry Reding
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On Mon, Jun 10, 2019 at 03:49:02PM +0530, Nagarjuna Kristam wrote:
> Configure the port capabilities based on usb_dr_mode settings.
>
> Based on work by JC Kuo .
>
> Signed-off-by: Nagarjuna Kristam
> Reviewed-by: JC Kuo
> Acked-by: Thierry Reding
> ---
> driver
drivers/phy/tegra/xusb.h | 2 ++
> 3 files changed, 123 insertions(+)
Acked-by: Thierry Reding
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hese are no longer showing up by default. That would explain it.
Anyway:
Acked-by: Thierry Reding
> diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
> index 294158113d62..dafc65911fc0 100644
> --- a/drivers/usb/host/xhci-tegra.c
> +++ b/drive
On Thu, May 16, 2019 at 12:09:32PM +0530, Nagarjuna Kristam wrote:
> Enable support for Nvidia XUSB device mode controller driver.
>
> Signed-off-by: Nagarjuna Kristam
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/ar
On Thu, May 16, 2019 at 12:09:31PM +0530, Nagarjuna Kristam wrote:
> This patch adds UDC driver for tegra XUSB 3.0 device mode controller.
> XUSB device mode controller supports SS, HS and FS modes
>
> Based on work by:
> Mark Kuo
> Andrew Bresticker
>
> Signed-off-by: Nagarjuna Kristam
>
usb/gadget/udc/tegra_xudc.c
Looks good to me, but please address Chunfeng's comments:
Acked-by: Thierry Reding
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On Thu, May 16, 2019 at 12:09:29PM +0530, Nagarjuna Kristam wrote:
> Tegra210 has one XUSB device mode controller, which can be operated
> HS and SS modes. Add DT support for XUSB device mode controller.
>
> Signed-off-by: Nagarjuna Kristam
> ---
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +
On Thu, May 16, 2019 at 12:09:28PM +0530, Nagarjuna Kristam wrote:
> Add device-tree binding documentation for the XUSB device mode controller
> present on Tegra210 SoC. This controller supports the USB 3.0
> specification.
>
> Signed-off-by: Nagarjuna Kristam
> ---
> .../devicetree/bindings/usb
e(struct tegra_xusb_padctl *padctl,
> + bool val)
> +{
> + if (padctl->soc->ops->vbus_override)
> + return padctl->soc->ops->vbus_override(padctl, val);
> +
> + return -ENOTSUPP;
On Thu, May 16, 2019 at 12:09:26PM +0530, Nagarjuna Kristam wrote:
> On Tegra210, usb2 only otg/peripheral ports dont work in device mode.
> They need an assosciated usb3 port to work in device mode. Identify
> an unused usb3 port and assign it as a fake USB3 port to USB2 only
> port whose mode is
> 1 file changed, 19 insertions(+), 3 deletions(-)
Acked-by: Thierry Reding
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On Thu, Apr 25, 2019 at 05:14:01PM +0200, Thierry Reding wrote:
> On Mon, Mar 11, 2019 at 04:41:52PM +0530, Nagarjuna Kristam wrote:
> > Add device-tree binding documentation for the XUSB device mode controller
> > present on tegra210 SoC. This controller supports USB 3.
On Mon, Mar 11, 2019 at 04:41:55PM +0530, Nagarjuna Kristam wrote:
> This patch adds UDC driver for tegra XUSB 3.0 device mode controller.
s/tegra/Tegra/
> XUSB device mode controller support SS, HS and FS modes
s/support/supports/ and terminate the sentence with a full-stop.
>
> Based on work
On Mon, Mar 11, 2019 at 04:41:52PM +0530, Nagarjuna Kristam wrote:
> Add device-tree binding documentation for the XUSB device mode controller
> present on tegra210 SoC. This controller supports USB 3.0 specification
Tegra210, please. "... supports the USB 3.0 ...". Also end sentences
with a fulls
b3_set_lfps_detect);
I think these changes should be a separate patch.
Thierry
>
> +int tegra_xusb_padctl_set_vbus_override(struct tegra_xusb_padctl *padctl,
> + bool val)
> +{
> + if (padctl->soc->ops->vbus_override)
On Mon, Mar 11, 2019 at 04:41:50PM +0530, Nagarjuna Kristam wrote:
> On Tegra210, usb2 only otg/peripheral ports dont work in device mode.
> They need an assosciated usb3 port to work in device mode. Identify
> an unused usb3 port and assign it as a fake USB3 port to USB2 only
> port whose mode is
On Mon, Mar 11, 2019 at 04:41:49PM +0530, Nagarjuna Kristam wrote:
> The device tree bindings document the "mode" property of "ports"
> subnodes, but the driver was not parsing the property. In preparation
> for adding role switching, parse the property at probe time and
> confgiure the port capabi
On Mon, Mar 11, 2019 at 04:41:52PM +0530, Nagarjuna Kristam wrote:
> Add device-tree binding documentation for the XUSB device mode controller
> present on tegra210 SoC. This controller supports USB 3.0 specification
>
> Based on work by Andrew Bresticker .
>
> Signed-off-by: Nagarjuna Kristam
>
On Thu, Apr 25, 2019 at 04:00:05PM +0300, Felipe Balbi wrote:
> Nagarjuna Kristam writes:
>
> > This patch adds UDC driver for tegra XUSB 3.0 device mode controller.
> > XUSB device mode controller support SS, HS and FS modes
> >
> > Based on work by:
> > Mark Kuo
> > Andrew Bresticker
> >
On Fri, Feb 15, 2019 at 11:48:37AM +0530, Nagarjuna Kristam wrote:
>
>
> On 13-02-2019 12:34, Nagarjuna Kristam wrote:
> >>> EXPORT_SYMBOL_GPL(tegra_xusb_padctl_usb3_set_lfps_detect);
> >>>
> >>> +int tegra_xusb_padctl_set_vbus_override(struct tegra_xusb_padctl *padctl)
> >>> +{
> >>> + if (pa
On Thu, Feb 14, 2019 at 08:22:34PM +0530, Nagarjuna Kristam wrote:
>
>
> On 04-02-2019 19:26, Thierry Reding wrote:
> > On Thu, Jan 03, 2019 at 03:34:58PM +0530, Nagarjuna Kristam wrote:
> >> This patch adds UDC driver for tegra XUSB 3.0 device mode controller.
> >
On Thu, Feb 14, 2019 at 08:26:52PM +0530, Nagarjuna Kristam wrote:
> >> + reg = <0x0 0x700d 0x0 0x8000>,
> >> + <0x0 0x700d8000 0x0 0x1000>,
> >> + <0x0 0x700d9000 0x0 0x1000>;
> >> + interrupts = <0 44 0x4>;
> >> + clocks = <&tegra_c
From: Thierry Reding
In order to be able to request an array of reset controls in acquired or
released mode, add the acquired flag to of_reset_control_array_get() and
pass the flag to subsequent calls of __of_reset_control_get().
Signed-off-by: Thierry Reding
---
drivers/reset/core.c
On Wed, Feb 20, 2019 at 05:16:12PM +0100, Greg Kroah-Hartman wrote:
> On Wed, Feb 20, 2019 at 02:48:41PM +0100, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > During initialization, the host and super-speed power domains will
> > contain an ERR_PTR() encoded e
From: Thierry Reding
During initialization, the host and super-speed power domains will
contain an ERR_PTR() encoded error code rather than being NULL. To
avoid a crash, use a !IS_ERR_OR_NULL() condition during cleanup.
Signed-off-by: Thierry Reding
---
drivers/usb/host/xhci-tegra.c | 4
On Thu, Feb 14, 2019 at 10:58:13AM +0530, Nagarjuna Kristam wrote:
>
>
> On 13-02-2019 18:46, Thierry Reding wrote:
> > On Wed, Feb 13, 2019 at 01:56:24PM +0100, Thierry Reding wrote:
> >> On Wed, Feb 13, 2019 at 04:08:15PM +0530, Nagarjuna Kristam wrote:
> >>
On Wed, Feb 13, 2019 at 01:56:24PM +0100, Thierry Reding wrote:
> On Wed, Feb 13, 2019 at 04:08:15PM +0530, Nagarjuna Kristam wrote:
> >
> >
> > On 04-02-2019 17:18, Thierry Reding wrote:
> > > On Thu, Jan 03, 2019 at 03:34:54PM +0530, Nagarjuna Kristam wro
On Wed, Feb 13, 2019 at 04:08:15PM +0530, Nagarjuna Kristam wrote:
>
>
> On 04-02-2019 17:18, Thierry Reding wrote:
> > On Thu, Jan 03, 2019 at 03:34:54PM +0530, Nagarjuna Kristam wrote:
> >> Add binding details regarding nvidia,usb3-port-fake
> >>
>
On Wed, Feb 13, 2019 at 12:34:39PM +0530, Nagarjuna Kristam wrote:
> Hi Thierry,
>
> On 04-02-2019 17:57, Thierry Reding wrote:
> > On Thu, Jan 03, 2019 at 03:34:52PM +0530, Nagarjuna Kristam wrote:
> >> Add support for XUSB device mode controller on Tegra210.
> >
On Fri, Jan 25, 2019 at 12:30:08PM +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> Extend the bindings to cover the set of features found in Tegra186.
>
> Signed-off-by: Thierry Reding
> ---
> .../devicetree/bindings/usb/nvidia,tegra124-xusb.txt | 4
On Thu, Jan 03, 2019 at 03:34:58PM +0530, Nagarjuna Kristam wrote:
> This patch adds UDC driver for tegra XUSB 3.0 device mode controller.
> XUSB device mode controller support SS, HS and FS modes
>
> Based on work by:
> Mark Kuo
> Andrew Bresticker
>
> Signed-off-by: Nagarjuna Kristam
> -
On Thu, Jan 03, 2019 at 03:34:55PM +0530, Nagarjuna Kristam wrote:
> Tegra210 has one XUSB device mode controller, which can be operated
> HS and SS modes. Add DT support for XUSB device mode controller.
>
> Signed-off-by: Nagarjuna Kristam
> ---
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 17 +
On Thu, Jan 03, 2019 at 03:34:56PM +0530, Nagarjuna Kristam wrote:
> Enable XUSB device mode driver for USB0 slot on Jetson TX1.
>
> Signed-off-by: Nagarjuna Kristam
> ---
> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/
On Thu, Jan 03, 2019 at 03:34:57PM +0530, Nagarjuna Kristam wrote:
> Add device-tree binding documentation for the XUSB device mode controller
> present on tegra210 SoC. This controller supports USB 3.0 specification
>
> Based on work by Andrew Bresticker .
>
> Signed-off-by: Nagarjuna Kristam
>
On Thu, Jan 03, 2019 at 03:34:52PM +0530, Nagarjuna Kristam wrote:
> Add support for XUSB device mode controller on Tegra210.
> Update PADCTL driver to set port cap based on DT config.
> Add code to handle property "nvidia,usb3-port-fake"
> Provide API's to control vbus override and utmi pad power
On Thu, Jan 03, 2019 at 03:34:54PM +0530, Nagarjuna Kristam wrote:
> Add binding details regarding nvidia,usb3-port-fake
>
> Signed-off-by: Nagarjuna Kristam
> ---
> Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
On Thu, Jan 03, 2019 at 03:34:51PM +0530, Nagarjuna Kristam wrote:
> Add driver for XUSB device mode controller available on Tegra
> Soc
>
> Patches 1-3 are phy driver changes to add support for device
> mode Patches 4-7 are changes related to XUSB device mode
> controller driver Patch 8 is to ena
From: JC Kuo
This commit adds Tegra186 XUSB host mode controller support. This is
very similar to the existing support for Tegra124 and Tegra210, except
that the number of ports and PHYs differs and the IPFS wrapper being
gone.
Signed-off-by: JC Kuo
Signed-off-by: Thierry Reding
---
drivers
From: Thierry Reding
Enable the relevant pads for XUSB support on P2771- and hook up the
USB supply voltage regulators to the ports.
Signed-off-by: Thierry Reding
---
.../boot/dts/nvidia/tegra186-p2771-.dts | 115 ++
.../arm64/boot/dts/nvidia/tegra186-p3310.dtsi
et to true. A future patch adding support for Tegra186 will set it to
false.
Signed-off-by: JC Kuo
Signed-off-by: Thierry Reding
---
drivers/usb/host/xhci-tegra.c | 43 +--
1 file changed, 26 insertions(+), 17 deletions(-)
diff --git a/drivers/usb/host/xhci
From: Thierry Reding
Extend the bindings to cover the set of features found in Tegra186.
Signed-off-by: Thierry Reding
---
.../devicetree/bindings/usb/nvidia,tegra124-xusb.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/nvidia
From: Thierry Reding
Adds the XUSB pad and XUSB controllers on Tegra186.
Signed-off-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 135 +++
1 file changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts
From: Thierry Reding
Various regulators were marked as always-on for Jetson TX2. At this
point, all of the regulators are properly hooked up, so this workaround
is no longer required.
Signed-off-by: Thierry Reding
---
.../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 23 ---
1
On Fri, Sep 14, 2018 at 03:01:22PM +0200, Greg KH wrote:
> On Fri, Sep 14, 2018 at 03:33:29PM +0300, Mathias Nyman wrote:
> > From: Thierry Reding
> >
> > The XUSB firmware header is in little endian byte order, so make the
> > fields __le32 and __le16 instead of u3
From: Thierry Reding
The XUSB firmware header is in little endian byte order, so make the
fields __le32 and __le16 instead of u32 and u16 to avoid warnings from
sparse when the fields are used with the endian-aware __le32_to_cpu()
and __le16_to_cpu() accessors, respectively.
Signed-off-by
On Fri, Aug 24, 2018 at 02:33:35PM -0700, Ajay Gupta wrote:
> Latest NVIDIA GPU card has USB Type-C interface. There is a
> Type-C controller which can be accessed over I2C.
>
> This driver add I2C bus driver to communicate with Type-C controller.
> I2C client driver will be part of USB Type-C UCS
>
> Changes since V1:
> - None
>
> drivers/usb/host/xhci-tegra.c | 68
> +++
> 1 file changed, 49 insertions(+), 19 deletions(-)
Seems fine to me:
Reviewed-by: Thierry Reding
Acked-by: Thierry Reding
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v, "failed to enable PHYs: %d\n", err);
> + goto disable_regulator;
> + }
> +
> + return 0;
> +
> +disable_regulator:
> + regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
> +disable_clk:
> + tegra_xusb_clk_disable(tegra);
> + return err;
> +}
> +
> +
There's an extra blank line here. Other than that, this looks very nice.
Reviewed-by: Thierry Reding
Acked-by: Thierry Reding
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Description: PGP signature
ore we enable the clocks, regulators and PHY and so prepare
> for adding runtime PM support, by moving the call to usb_create_hcd()
> before we enable the hardware.
>
> Signed-off-by: Jon Hunter
Acked-by: Thierry Reding
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On Thu, Mar 08, 2018 at 09:31:07PM +, Jon Hunter wrote:
>
> On 01/03/18 14:18, Mathias Nyman wrote:
> > On 14.02.2018 18:34, Jon Hunter wrote:
> >> Add runtime PM support to the Tegra XHCI driver and move the function
> >> calls to enable/disable the clocks, regulators and PHY into the runtime
On Wed, Jul 19, 2017 at 05:59:08PM +0200, Philipp Zabel wrote:
> From: Vivek Gautam
>
> Make use of of_reset_control_array_get_exclusive() to manage
> an array of reset controllers available with the device.
>
> Cc: Jon Hunter
> Cc: Thierry Reding
> Signed-off-b
On Tue, Dec 19, 2017 at 05:58:07AM +0300, Dmitry Osipenko wrote:
> USB Ethernet gadget now works on Tegra30.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/usb/chipidea/ci_hdrc_tegra.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Thierry Redin
On Mon, Dec 11, 2017 at 02:07:38AM +0300, Dmitry Osipenko wrote:
> UTMI pads are shared by USB controllers and reset of UTMI pads is shared
> with the reset of USB1 controller. Currently reset of UTMI pads is done by
> the EHCI driver and ChipIdea UDC works because EHCI driver always happen
> to be
On Mon, Dec 11, 2017 at 02:10:00AM +0300, Dmitry Osipenko wrote:
> UDC driver won't probe without Tegra's PHY, hence select it in the
> Kconfig.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/usb/chipidea/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/usb/chipidea/
On Mon, Dec 11, 2017 at 02:09:59AM +0300, Dmitry Osipenko wrote:
> Add Kconfig entry so that other drivers other than ehci-tegra
> (like ChipIdea) could add Tegra's PHY to build dependencies.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/usb/host/Kconfig | 2 +-
> drivers/usb/phy/Kconfig |
On Mon, Dec 11, 2017 at 01:55:35AM +0300, Dmitry Osipenko wrote:
> This fixes "utmi_phy_clk_enable: timeout waiting for phy to stabilize"
> error message.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/usb/phy/phy-tegra-usb.c | 13 -
> 1 file changed, 4 insertions(+), 9 deletions
On Mon, Dec 11, 2017 at 02:07:37AM +0300, Dmitry Osipenko wrote:
> Tegra's PHY driver has a mix of pr_err() and dev_err(), let's switch to
> dev_err() and use common errors message formatting across the driver for
> consistency.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/usb/phy/phy-tegr
1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Thierry Reding
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V1:
> - Added fixes tag
> - Added test in PHY enable to see if clock is already on before enabling
>
> drivers/usb/phy/phy-tegra-usb.c | 17 +
> 1 file changed, 17 insertions(+)
Acked-by: Thierry Reding
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Description: PGP signature
On Thu, Jul 06, 2017 at 02:20:04AM +0300, Dmitry Osipenko wrote:
> On 06.07.2017 01:54, Stephen Warren wrote:
> > On 07/05/2017 04:13 PM, Dmitry Osipenko wrote:
> >> On 05.07.2017 23:31, Stephen Warren wrote:
> >>> On 07/05/2017 11:19 AM, Dmitry Osipenko wrote:
>
gt; sound/soc/codecs/twl4030.c | 2 +-
> 25 files changed, 26 insertions(+), 26 deletions(-)
> rename include/linux/{i2c => mfd}/twl.h (100%)
I didn't see this get applied yet, so just in case anyone was waiting
for me (this is trivial, so I don't think there's a need):
Acked-by: Thierry Reding
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Description: PGP signature
drivers/usb/host/xhci-tegra.c |1 -
> 2 files changed, 2 deletions(-)
For Tegra:
Tested-by: Thierry Reding
Acked-by: Thierry Reding
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Description: PGP signature
On Mon, Jan 30, 2017 at 07:45:21AM +0100, Greg Kroah-Hartman wrote:
> On Mon, Jan 30, 2017 at 10:36:29AM +0530, Shailendra Verma wrote:
> > of_device_get_match_data could return NULL, and so can cause
> > a NULL pointer dereference later.
> >
> > Signed-off-by: Shailendra Verma
> > ---
> > drive
On Thu, Aug 25, 2016 at 07:39:09PM +0200, Wolfram Sang wrote:
> All kmalloc-based functions print enough information on failures.
>
> Signed-off-by: Wolfram Sang
> ---
> drivers/usb/host/xhci-tegra.c | 1 -
> 1 file changed, 1 deletion(-)
Acked-by: Thierry Reding
signatu
From: Thierry Reding
Override the compatible string of the first USB controller to enable
device mode.
Signed-off-by: Thierry Reding
---
arch/arm/boot/dts/tegra30-beaver.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts
b/arch/arm/boot
From: Thierry Reding
All Tegra SoC generations from Tegra20 through Tegra124 have a ChipIdea
USB device controller. This set of patches adds very rudimentary support
for it to the existing ChipIdea driver and enables them on the set of
boards that I could easily test on.
I'm sending this o
From: Thierry Reding
Override the compatible string of the first USB controller to enable
device mode.
Signed-off-by: Thierry Reding
---
arch/arm/boot/dts/tegra114-dalmore.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
b/arch/arm
From: Thierry Reding
All of these Tegra SoC generations have a ChipIdea UDC IP block that can
be used for device mode communication with a host. Implement rudimentary
support that doesn't allow switching between host and device modes.
Signed-off-by: Thierry Reding
---
drivers/usb/chi
From: Thierry Reding
Override the compatible string of the first USB controller to enable
device mode.
Signed-off-by: Thierry Reding
---
arch/arm/boot/dts/tegra20-trimslice.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts
b/arch/arm/boot/dts
From: Thierry Reding
Override the compatible string of the first USB controller to enable
device mode.
Signed-off-by: Thierry Reding
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124
On Thu, May 26, 2016 at 05:23:30PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Starting with commit 0b52297f2288 ("reset: Add support for shared reset
> controls") there is a reference count for reset control assertions. The
> goal is to allow resets to be s
From: Thierry Reding
Starting with commit 0b52297f2288 ("reset: Add support for shared reset
controls") there is a reference count for reset control assertions. The
goal is to allow resets to be shared by multiple devices and an assert
will take effect only when all instances have as
From: Thierry Reding
There are three EHCI controllers on Tegra SoCs, each with its own reset
line. However, the first controller contains a set of UTMI configuration
registers that are shared with its siblings. These registers will only
be reset as part of the first controller's reset
On Wed, May 04, 2016 at 11:14:50AM -0600, Stephen Warren wrote:
> On 05/04/2016 08:39 AM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > There are three EHCI controllers on Tegra SoCs, each with its own reset
> > line. However, the first controller contains
On Wed, May 04, 2016 at 11:23:20AM -0600, Stephen Warren wrote:
> On 05/04/2016 08:40 AM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Starting with commit 0b52297f2288 ("reset: Add support for shared reset
> > controls") there is a reference co
On Wed, May 04, 2016 at 07:22:54PM +0200, Philipp Zabel wrote:
> Hi Thierry,
>
> Am Mittwoch, den 04.05.2016, 16:40 +0200 schrieb Thierry Reding:
> > From: Thierry Reding
> >
> > Starting with commit 0b52297f2288 ("reset: Add support for shared reset
> >
On Wed, May 04, 2016 at 07:57:10AM -0700, Greg Kroah-Hartman wrote:
> On Wed, May 04, 2016 at 04:39:59PM +0200, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > There are three EHCI controllers on Tegra SoCs, each with its own reset
> > line. However, the first c
From: Thierry Reding
Starting with commit 0b52297f2288 ("reset: Add support for shared reset
controls") there is a reference count for reset control assertions. The
goal is to allow resets to be shared by multiple devices and an assert
will take effect only when all instances have as
On Tue, May 03, 2016 at 03:16:56PM -0400, Alan Stern wrote:
> On Tue, 3 May 2016, Thierry Reding wrote:
>
> > From: Thierry Reding
> >
> > Starting with commit 0b52297f2288 ("reset: Add support for shared reset
> > controls") there is a reference count fo
From: Thierry Reding
There are three EHCI controllers on Tegra SoCs, each with its own reset
line. However, the first controller contains a set of UTMI configuration
registers that are shared with its siblings. These registers will only
be reset as part of the first controller's reset
On Wed, May 04, 2016 at 04:22:02PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Starting with commit 0b52297f2288 ("reset: Add support for shared reset
> controls") there is a reference count for reset control assertions. The
> goal is to allow resets to be s
From: Thierry Reding
There are three EHCI controllers on Tegra SoCs, each with its own reset
line. However, the first controller contains a set of UTMI configuration
registers that are shared with its siblings. These registers will only
be reset as part of the first controller's reset
From: Thierry Reding
Starting with commit 0b52297f2288 ("reset: Add support for shared reset
controls") there is a reference count for reset control assertions. The
goal is to allow resets to be shared by multiple devices and an assert
will take effect only when all instances have as
On Tue, May 03, 2016 at 08:05:55PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Starting with commit 0b52297f2288 ("reset: Add support for shared reset
> controls") there is a reference count for reset control assertions. The
> goal is to allow resets to be s
From: Thierry Reding
Starting with commit 0b52297f2288 ("reset: Add support for shared reset
controls") there is a reference count for reset control assertions. The
goal is to allow resets to be shared by multiple devices and an assert
will take effect only when all instances have as
.
Andrew Bresticker (1):
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
Thierry Reding (22):
Merge branch 'for-4.7/clk' into for-4.7/phy
phy: core: Allow children node to be overridden
d
This set of patches introduces a driver for the XUSB controller found on
NVIDIA Tegra SoCs. When loaded with a firmware (available via the linux-
firmware repository), it provides an XHCI-compatible interface.
Thierry Reding (5
that replaces the existing EHCI controllers.
Support is enabled on Venice2, Jetson TK1 and Nyan-based Chromebooks.
Andrew Bresticker (1):
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
Thierry Redin
).
Thierry Reding (6):
Merge branch 'for-4.7/clk' into for-4.7/phy
phy: core: Allow children node to be overridden
dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding
dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support
phy: Add
update the Tegra PCIe host bridge controller device tree
bindings and driver to cope with per-lane PHYs on Tegra124 and later.
Thierry Reding (3):
Merge branch 'for-4.7/phy' into for-4.7/pci
dt-bindings: pci: teg
Hi everyone,
This is a fairly complicated series of pull requests because of the
dependencies involved. The goal is to take all of the patches through
the ARM-SoC tree but I'm sending out these individual pull requests
to document this. Also, if these branches were starting to cause
conflicts they
On Wed, Apr 06, 2016 at 07:08:24PM +0200, Thierry Reding wrote:
[...]
> I attached what I came up with. It extends the OF PHY provider registry
> by allowing an additional node to be specified that if specified will
> serve as the parent for the child lookup (and hence overrides the
>
On Fri, Mar 04, 2016 at 05:19:34PM +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs.
> This hardware block used to be exposed as a pin controller, but it turns
> out that this isn't a good fit. T
On Tue, Mar 15, 2016 at 10:01:25AM +0100, Linus Walleij wrote:
> On Fri, Mar 4, 2016 at 5:19 PM, Thierry Reding
> wrote:
>
> > From: Thierry Reding
> >
> > This is an old version of the binding that isn't flexible enough to
> > describe all aspects of the
On Tue, Mar 15, 2016 at 10:01:25AM +0100, Linus Walleij wrote:
> On Fri, Mar 4, 2016 at 5:19 PM, Thierry Reding
> wrote:
>
> > From: Thierry Reding
> >
> > This is an old version of the binding that isn't flexible enough to
> > describe all aspects of the
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