Re: [PATCH 2/2] [RFC] usb: dwc3: using the maximum_speed to determine if the usb3 phy is needed

2013-07-10 Thread Ruchika Kharwar
On 07/10/2013 06:46 AM, Felipe Balbi wrote: Hi, On Sat, Jul 06, 2013 at 07:53:57AM -0500, Ruchika Kharwar wrote: When the initialization of usb3 phy fails, when enabled in the system the dwc3_probe deferral is further qualified by the maximum speed. In devices such as dra7xx

Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-07-08 Thread Ruchika Kharwar
On 07/08/2013 02:28 AM, Felipe Balbi wrote: On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote: Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Nikhil

[PATCH 2/2] [RFC] usb: dwc3: using the maximum_speed to determine if the usb3 phy is needed

2013-07-06 Thread Ruchika Kharwar
on http://www.spinics.net/lists/linux-usb/msg88627.html Signed-off-by: Ruchika Kharwar --- drivers/usb/dwc3/core.c |7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 7b98e4f..05f2205 100644 --- a/drivers/usb/dwc3

[PATCH 1/2] usb: dwc3: adapt to use dr_mode device tree helper

2013-07-06 Thread Ruchika Kharwar
This patch adapts the dwc3 to use the device tree helper "of_usb_get_dr_mode" for the mode of operation of the dwc3 instance being probed. Signed-off-by: Ruchika Kharwar --- drivers/usb/dwc3/core.c | 51 +-- drivers/usb/dwc3/core.h |

Re: [PATCH 2/5] arm: dts: am33xx: add USB phy nodes

2013-07-05 Thread Ruchika Kharwar
On 07/05/2013 08:32 AM, Sebastian Andrzej Siewior wrote: The memory address contains three pieces that is the reset module which is currently the only one used and two other pices which seem interresting based on what the register. Please fix typos "pices.. interresting".. also the description

Re: [PATCH] [RFC] usb: dwc3: removal of assumption that usb3 phy always present

2013-07-05 Thread Ruchika Kharwar
On 07/04/2013 01:26 AM, Ruchika Kharwar wrote: DRA7XX has several USB OTG subsystems. USB_OTG_SS1 includes a USB1 and USB2 phy. USB_OTG_SS2 includes only a USB2 phy. This patch allows the dwc3 probe to continue if a usb3_phy is not found. The need for this will go away as soon as

[PATCH] [RFC] usb: dwc3: removal of assumption that usb3 phy always present

2013-07-03 Thread Ruchika Kharwar
: Ruchika Kharwar --- drivers/usb/dwc3/core.c | 38 -- drivers/usb/dwc3/gadget.c | 11 --- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 358375e..feea92d 100644 --- a

[PATCH] usb: dwc3: fix the error returned with usb3_phy failure

2013-07-03 Thread Ruchika Kharwar
When there is an error with the usb3_phy probe or absence, the error returned is erroneously for usb2_phy. Signed-off-by: Ruchika Kharwar --- drivers/usb/dwc3/core.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index

[PATCH] usb: phy: omap-usb3: fix dpll clock index

2013-07-03 Thread Ruchika Kharwar
Correction of the omap_usb3_dpll_params array when the sys_clk_rate is 20MHz. Signed-off-by: Nikhil Devshatwar Signed-off-by: Ruchika Kharwar --- drivers/usb/phy/phy-omap-usb3.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb

[PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-06-21 Thread Ruchika Kharwar
Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Nikhil Devshatwar Signed-off-by: Ruchika Kharwar --- drivers/usb/phy/phy-omap-usb3.c |7 ++- 1 file changed, 6

Re: [PATCH 0/5] dwc3: omap: adapt dwc3 to use extcon framework

2013-06-04 Thread Ruchika Kharwar
Kishon, What is the expectation when there is no palmas tied to dwc3/dwc3-omap ? Thank you Regards Ruchika On 06/03/2013 11:13 AM, Kishon Vijay Abraham I wrote: The first three patches deals with cleanup of extcon inorder to get through compilation without any issues. It also adds an API to get

Re: [PATCH] usb: dwc3: Addition of "dr_mode" dt property.

2013-05-30 Thread Ruchika Kharwar
On 05/30/2013 03:35 PM, Dan Murphy wrote: Fix spelling in my own comments On 05/30/2013 03:31 PM, Dan Murphy wrote: On 05/30/2013 03:14 PM, Ruchika Kharwar wrote: This patch adds an optional parameter "dr_mode" to the dwc3 core device node. In the case the compile flag fo

[PATCH] usb: dwc3: Addition of "dr_mode" dt property.

2013-05-30 Thread Ruchika Kharwar
his optional flag or specifies it superfluously to "drd" the functionality will be that of a dual role device. Signed-off-by: Ruchika Kharwar --- Documentation/devicetree/bindings/usb/dwc3.txt |3 ++- drivers/usb/dwc3/core.c| 20 +--- 2 file

[PATCH] usb: dwc3: Addition of "dr_mode" dt property.

2013-05-30 Thread Ruchika Kharwar
his optional flag or specifies it superfluously to "drd" the functionality will be that of a dual role device. Signed-off-by: Ruchika Kharwar --- Documentation/devicetree/bindings/usb/dwc3.txt |3 ++- drivers/usb/dwc3/core.c| 21 + 2 file

[PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

2013-05-30 Thread Ruchika Kharwar
Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Ruchika Kharwar --- drivers/usb/phy/phy-omap-usb3.c |7 ++- 1 files changed, 6 insertions(+), 1 deletions

[PATCH] usb: dwc3: Addition of "dr_mode" dt property.

2013-05-30 Thread Ruchika Kharwar
This patch adds the possibility of the "mode" being specified in a device tree. This allows the scenario when there maybe multiple USB subsystems operating in different modes. Signed-off-by: Ruchika Kharwar --- Documentation/devicetree/bindings/usb/dwc3.txt |3 ++- drivers/usb/d