/0x18
This disables the regulator if enabled on suspend, and the reverse on
resume.
Fixes: c3376f72 ("usb: dwc3: Add Amlogic G12A DWC3 glue")
Reported-by: Kevin Hilman
Signed-off-by: Neil Armstrong
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 14 +-
1 file changed, 13 insert
devm_platform_ioremap_resource(pdev, 0);
> if (IS_ERR(base))
> return PTR_ERR(base);
>
>
Acked-by: Neil Armstrong
On 07/03/2019 03:02, Chunfeng Yun wrote:
> Hi,
> On Mon, 2019-03-04 at 11:38 +0100, Neil Armstrong wrote:
>> Adds support for Amlogic G12A USB Control Glue HW.
>>
>> The Amlogic G12A SoC Family embeds 2 USB Controllers :
>> - a DWC3 IP configured as Host for USB2 and
On 06/03/2019 22:04, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong
> wrote:
> [...]
>> +static int phy_g12a_usb3_init(struct phy *phy)
>> +{
>> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvda
On 06/03/2019 22:00, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong
> wrote:
> [...]
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
> the
On 06/03/2019 22:27, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong
> wrote:
>>
>> Adds the bindings for the Amlogic G12A USB Glue HW.
>>
>> The Amlogic G12A SoC Family embeds 2 USB Controllers :
>> - a DW
On 05/03/2019 22:42, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 4, 2019 at 11:38 AM Neil Armstrong
> wrote:
>>
>> Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings.
>>
>> This PHY can provide exclusively USB3 or PCIE support on sh
removing the NULL test
- Added optional vbus regulator handling
[1] https://lkml.kernel.org/r/20190212151413.24632-1-narmstr...@baylibre.com
Neil Armstrong (8):
dt-bindings: phy: Add Amlogic G12A USB2 PHY Bindings
dt-bindings: phy: Add Amlogic G12A USB3+PCIE Combo PHY Bindings
dt-bindings
Adds the specific compatible string for the DWC2 IP found in the
Amlogic G12A SoC Family.
Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a
Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings.
This PHY can provide exclusively USB3 or PCIE support on shared I/Os.
Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
---
.../bindings/phy/meson-g12a-usb3-pcie-phy.txt | 22 +++
1 file changed, 22
Add the Amlogic G12A Family USB2 OTG PHY Bindings
The PHY can work in host or peripheral modes depending on it's position.
Configuration of the mode is part of the USBCTRL registers which are
outside of the PHY registers.
Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
Rev
controls the
interface with the PHY, not the DWC3 controller.
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/usb/amlogic,dwc3.txt | 88 +++
1 file changed, 88 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
b/Documentation/devicetree
ff-by: Neil Armstrong
---
drivers/phy/amlogic/Kconfig | 11 ++
drivers/phy/amlogic/Makefile | 1 +
drivers/phy/amlogic/phy-meson-g12a-usb2.c | 190 ++
3 files changed, 202 insertions(+)
create mode 100644 drivers/phy/amlogic/phy-meson-g12a-usb2.c
via a debugfs interface. The IRQ mode change detect is yet to be added
in a future patchset, mainly due to lack of hardware to validate on.
Signed-off-by: Neil Armstrong
---
drivers/usb/dwc3/Kconfig | 10 +
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-meson-g12a.c
This patchs sets the params for the DWC2 Controller found in the
Amlogic G12A SoC family.
It mainly sets the settings reported incorrect by the driver,
leaving the remaining detected automatically by the driver and
provided by the DT node.
Signed-off-by: Neil Armstrong
---
drivers/usb/dwc2
This adds support for the shared USB3 + PCIE PHY found in the
Amlogic G12A SoC Family.
It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of
the board.
Selection is done by the #phy-cells, making the mode static and exclusive.
Signed-off-by: Neil Armstrong
---
drivers/phy
Hi,
On 02/03/2019 11:29, Martin Blumenstingl wrote:
> Hi Neil,
>
>>> +static int dwc3_meson_g12a_debugfs_init(struct dwc3_meson_g12a *priv)
>>> +{
>>> + priv->root = debugfs_create_dir("dwc3-meson-g12a", NULL);
>>> + if (IS_ERR(priv->root))
>>> + return PTR_ERR(priv->roo
On 28/02/2019 17:29, Rob Herring wrote:
> On Tue, Feb 12, 2019 at 04:14:09PM +0100, Neil Armstrong wrote:
>> Adds the bindings for the Amlogic G12A USB Glue HW.
>>
>> The Amlogic G12A SoC Family embeds 2 USB Controllers :
>> - a DWC3 IP configured as Host for U
Hi Martin,
On 17/02/2019 23:24, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Tue, Feb 12, 2019 at 4:15 PM Neil Armstrong
> wrote:
>>
>> This adds support for the USB2 PHY found in the Amlogic G12A SoC Family.
>>
>> It supports Host and/or Peripheral mode
On 17/02/2019 23:03, Martin Blumenstingl wrote:
> On Tue, Feb 12, 2019 at 4:15 PM Neil Armstrong
> wrote:
>>
>> Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings.
>>
>> This PHY can provide exclusively USB3 or PCIE support on shared I/Os.
>>
>>
to be added
in a future patchset, mainly due to lack of hardware to validate on.
Neil Armstrong (8):
dt-bindings: phy: Add Amlogic G12A USB2 PHY Bindings
dt-bindings: phy: Add Amlogic G12A USB3+PCIE Combo PHY Bindings
dt-bindings: usb: dwc2: Add Amlogic G12A DWC2 Compatible
dt-bindings
Add the Amlogic G12A Family USB2 OTG PHY Bindings
Signed-off-by: Neil Armstrong
---
.../bindings/phy/meson-g12a-usb2-phy.txt | 22 +++
1 file changed, 22 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt
diff --git a
Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings.
This PHY can provide exclusively USB3 or PCIE support on shared I/Os.
Signed-off-by: Neil Armstrong
---
.../bindings/phy/meson-g12a-usb3-pcie-phy.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
interface
with the PHY, not the DWC3 controller.
The PHY interconnect is handled into ports subnodes, which eases describing
which PHY is enabled (like the USB3 shared PHY) and futures layouts on
derivatives of the G12A Family.
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/usb/amlogic
Adds the specific compatible string for the DWC2 IP found in the
Amlogic G12A SoC Family.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt
b/Documentation
be added
in a future patchset, mainly due to lack of hardware to validate on.
Signed-off-by: Neil Armstrong
---
drivers/usb/dwc3/Kconfig | 9 +
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-meson-g12a.c | 650 +
3 files changed, 660
This adds support for the shared USB3 + PCIE PHY found in the
Amlogic G12A SoC Family.
It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of
the board.
Selection is done by the #phy-cells, making the mode static and exclusive.
Signed-off-by: Neil Armstrong
---
drivers/phy
This patchs sets the params for the DWC2 Controller found in the
Amlogic G12A SoC family.
It mainly sets the settings reported incorrect by the driver,
leaving the remaining detected automatically by the driver and
provided by the DT node.
Signed-off-by: Neil Armstrong
---
drivers/usb/dwc2
ff-by: Neil Armstrong
---
drivers/phy/amlogic/Kconfig | 12 ++
drivers/phy/amlogic/Makefile | 1 +
drivers/phy/amlogic/phy-meson-g12a-usb2.c | 191 ++
3 files changed, 204 insertions(+)
create mode 100644 drivers/phy/amlogic/phy-meson-g12a-usb2.c
n-gxl-usb2 driver
https://lkml.kernel.org/r/20180128202245.25021-1-martin.blumensti...@googlemail.com
- initialize (multiple) PHYs for a HCD V11
https://lkml.kernel.org/r/20180303214309.25643-1-martin.blumensti...@googlemail.com
- Meson GXL USB3 PHY driver V4
https://lkml.kernel.org/r/20180303184700.21480-1-mart
| 1 +
> drivers/usb/host/ohci-omap.c | 1 +
> drivers/usb/host/ohci-platform.c | 56 +---
> drivers/usb/host/xhci-mtk.c| 98 +
> drivers/usb/host/xhci-plat.c | 1 +
> inclu
s on the root-hub
> usb: core: hcd: integrate the PHY roothub wrapper
>
> .../devicetree/bindings/usb/usb-roothub.txt| 46 ++
> Documentation/devicetree/bindings/usb/usb-xhci.txt | 7 +
> drivers/usb/core/Makefile | 2 +-
> drivers/usb/core
On 18/10/2017 11:05, Arnd Bergmann wrote:
> On Tue, Oct 17, 2017 at 11:19 PM, Martin Blumenstingl
> wrote:
>>> Ok, very good!
>>>
is there anything else you want me to test?
>>>
>>> What about the same dtb when run on a kernel without your
>>> patch series? Does that work as well, or are your
Hi Mason,
On 12/02/2016 07:00 PM, Mason wrote:
> [ Fix incorrect address for Felipe ]
>
> On 02/12/2016 14:46, Neil Armstrong wrote:
>
>> On 12/02/2016 11:24 AM, Mason wrote:
>>
>>> (Sad face) All the documentation I have is in front of me, and nothing
>&
On 06/28/2016 11:58 PM, Stephen Boyd wrote:
> Quoting Neil Armstrong (2016-06-28 01:49:37)
>> On 06/26/2016 09:28 AM, Stephen Boyd wrote:
>>> + uphy->cal_sleep_clk = clk = devm_clk_get(&ulpi->dev, "cal_sleep");
>>> + if (IS_ERR(clk))
>>
On 06/26/2016 09:28 AM, Stephen Boyd wrote:
> The HSIC USB controller on qcom SoCs has an integrated all
> digital phy controlled via the ULPI viewport.
>
> Cc: Kishon Vijay Abraham I
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> .../devicetree/bindings/phy/qcom,usb-hsic-phy.txt | 60
On 06/17/2016 06:39 PM, Stephen Boyd wrote:
> On 06/17/2016 03:25 AM, Neil Armstrong wrote:
>> In order to support the Qualcomm MDM9615 in the Sierra Wireless WP8548
>> Modules, add the Qualcomm HSIC USB PHY used inside the MDM9615 SoC.
>>
>> This patchset is part of a
Add support for the HSIC PHY present in the Qualcomm MSM9615 SoC.
This PHY is also present on other SoCs and would need some changes.
Signed-off-by: Neil Armstrong
---
drivers/usb/phy/Kconfig | 13 +
drivers/usb/phy/Makefile| 1 +
drivers/usb/phy/phy-qcom-hsic-usb.c
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/phy/qcom,usb-hsic-phy.txt | 95 ++
1 file changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hsic
In order to support the Qualcomm MDM9615 in the Sierra Wireless WP8548
Modules, add the Qualcomm HSIC USB PHY used inside the MDM9615 SoC.
This patchset is part of a global SoC + Module + Board support for the
Sierra Wireless mangOH Board support with the WP8548 module.
Neil Armstrong (2):
usb
(or even Evatronix
employees who worked on this IP before being in Cadence portfolio)
to push this driver upstream by testing it on a real HW or even FPGA.
I hope this message in a bottle will get read !
Regards,
Neil
On 11/16/2015 05:11 PM, Felipe Balbi wrote:
>
> Hi,
>
> Ne
.
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/usb/cadence-hsudc.txt | 55 +
drivers/usb/gadget/udc/Kconfig | 15 +
drivers/usb/gadget/udc/Makefile|1 +
drivers/usb/gadget/udc/cadence_hsudc.c | 2136
I get stuck
with weird HW beheviours
Signed-off-by: Neil Armstrong
---
drivers/usb/dwc2/core.h | 14 +++
drivers/usb/dwc2/gadget.c | 267 +++--
2 files changed, 221 insertions(+), 60 deletions(-)
This is mainly an RFC in order to make this driv
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