[PATCH/RFC] usb: dwc2: awake rt305x USB controller

2018-07-20 Thread John Crispin
From: Serge Vasilugin The Ralink uboot sets the USB controller into sleep mode. This patch checks this condition and awakes controller before any register access. Signed-off-by: Serge Vasilugin Signed-off-by: John Crispin --- Hi, we have been carrying this patch inside OpenWrt for half a

[PATCH] usb: make the MTK XHCI driver compile for older MIPS SoCs

2016-12-20 Thread John Crispin
The MIPS based MT7621 shares the same XHCI core as the newer generation of ARM based SoCs. The driver works out of the box and we only need to make it buildable in Kconfig. Signed-off-by: John Crispin --- drivers/usb/host/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions

Re: [PATCH v2 4/5] xhci: mediatek: support MTK xHCI host controller

2015-07-13 Thread John Crispin
Hi there is a cross dependency between the modules. xhci-mtk.ko requires xhci.ko to be loaded. however this will look for xhci_mtk_add_ep_quirk() which is part of xhci-mtk. the modules will build but are not run time loadable. John On 08/07/2015 11:41, Chunfeng Yun wrote: > MTK xhci host

Re: [RFC PATCH] usb: dwc2: Use platform endianness when accessing registers

2015-01-21 Thread John Crispin
Hi, small nitpick On 21/01/2015 19:27, Antti Seppälä wrote: > This patch switches calls to readl/writel to their > __raw_readl/__raw_writel equivalents which preserve platform endianness. > > This patch is necessary to access dwc2 registers correctly on big endian > systems such as mips. Then dw

[PATCH V2] USB: dwc2: add support for the reset_controller api

2014-10-16 Thread John Crispin
We need this for dwc2 to work on older ralink SoC like the rt3052. Without, we see the following when loading the driver: [0.76] dwc2 101c.usb: Bad value for GSNPSID: 0x Signed-off-by: John Crispin --- Changes since V1 * move the OF lookup call into the platform code * add

Re: [PATCH] USB: dwc2: add a call to device_reset_optional()

2014-10-14 Thread John Crispin
On 14/10/2014 21:54, Paul Zimmerman wrote: >> From: linux-usb-ow...@vger.kernel.org >> [mailto:linux-usb-ow...@vger.kernel.org] On Behalf Of John Crispin >> Sent: Friday, October 10, 2014 10:27 AM >> >> We need this for dwc2 to work on older ralink SoC like the rt3

[PATCH] USB: dwc2: add a call to device_reset_optional()

2014-10-10 Thread John Crispin
We need this for dwc2 to work on older ralink SoC like the rt3052. Signed-off-by: John Crispin --- drivers/usb/dwc2/hcd.c |6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 4d918ed..8b5f966 100644 --- a/drivers/usb/dwc2/hcd.c +++ b

Re: [PATCH] USB: phy: add ralink SoC driver

2014-10-10 Thread John Crispin
On 10/10/2014 15:58, Felipe Balbi wrote: > On Fri, Oct 10, 2014 at 12:20:01PM +0200, John Crispin wrote: >> RT3352, RT5350 and the MT762x SoCs all have a usb phy that we need to setup. >> >> Signed-off-by: John Crispin > new PHY drivers only on drivers/phy ;-) > i that

[PATCH] USB: phy: add ralink SoC driver

2014-10-10 Thread John Crispin
RT3352, RT5350 and the MT762x SoCs all have a usb phy that we need to setup. Signed-off-by: John Crispin --- drivers/usb/phy/Kconfig |8 ++ drivers/usb/phy/Makefile |1 + drivers/usb/phy/phy-ralink.c | 192 ++ 3 files changed, 201

Re: dwc2: Invalid (?) initialization of PCGCTL register

2013-07-16 Thread John Crispin
Hi, Simply resetting the PCGCTL register in hcd_init or somewhere around there fixes the problem. However, John suggested an even more generic problem: using the kernel-wide reset controller driver to completely reset the dwc controller before initializing it (by calling device_reset()). On the