From: Serge Vasilugin
The Ralink uboot sets the USB controller into sleep mode. This patch checks
this condition and awakes controller before any register access.
Signed-off-by: Serge Vasilugin
Signed-off-by: John Crispin
---
Hi,
we have been carrying this patch inside OpenWrt for half a
The MIPS based MT7621 shares the same XHCI core as the newer generation of
ARM based SoCs. The driver works out of the box and we only need to make it
buildable in Kconfig.
Signed-off-by: John Crispin
---
drivers/usb/host/Kconfig |4 ++--
1 file changed, 2 insertions(+), 2 deletions
Hi
there is a cross dependency between the modules. xhci-mtk.ko requires
xhci.ko to be loaded. however this will look for xhci_mtk_add_ep_quirk()
which is part of xhci-mtk. the modules will build but are not run time
loadable.
John
On 08/07/2015 11:41, Chunfeng Yun wrote:
> MTK xhci host
Hi,
small nitpick
On 21/01/2015 19:27, Antti Seppälä wrote:
> This patch switches calls to readl/writel to their
> __raw_readl/__raw_writel equivalents which preserve platform endianness.
>
> This patch is necessary to access dwc2 registers correctly on big endian
> systems such as mips. Then dw
We need this for dwc2 to work on older ralink SoC like the rt3052. Without, we
see the following when loading the driver:
[0.76] dwc2 101c.usb: Bad value for GSNPSID: 0x
Signed-off-by: John Crispin
---
Changes since V1
* move the OF lookup call into the platform code
* add
On 14/10/2014 21:54, Paul Zimmerman wrote:
>> From: linux-usb-ow...@vger.kernel.org
>> [mailto:linux-usb-ow...@vger.kernel.org] On Behalf Of John Crispin
>> Sent: Friday, October 10, 2014 10:27 AM
>>
>> We need this for dwc2 to work on older ralink SoC like the rt3
We need this for dwc2 to work on older ralink SoC like the rt3052.
Signed-off-by: John Crispin
---
drivers/usb/dwc2/hcd.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 4d918ed..8b5f966 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b
On 10/10/2014 15:58, Felipe Balbi wrote:
> On Fri, Oct 10, 2014 at 12:20:01PM +0200, John Crispin wrote:
>> RT3352, RT5350 and the MT762x SoCs all have a usb phy that we need to setup.
>>
>> Signed-off-by: John Crispin
> new PHY drivers only on drivers/phy ;-)
>
i that
RT3352, RT5350 and the MT762x SoCs all have a usb phy that we need to setup.
Signed-off-by: John Crispin
---
drivers/usb/phy/Kconfig |8 ++
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/phy-ralink.c | 192 ++
3 files changed, 201
Hi,
Simply resetting the PCGCTL register in hcd_init or somewhere around
there fixes the problem. However, John suggested an even more generic
problem: using the kernel-wide reset controller driver to completely
reset the dwc controller before initializing it (by calling
device_reset()). On the
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