Add a DT binding documentation of XS-PHY for MediaTek SoCs
with USB3.1 GEN2 controller
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/phy/phy-mtk-xsphy.txt | 110
1 file changed, 110 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-m
>From 2ca1243f228633ca9dd96d3e4068af9e2936cd51 Mon Sep 17 00:00:00 2001
From: Chunfeng Yun
Date: Thu, 10 May 2018 13:55:52 +0800
Subject: [PATCH v3 0/2] Add MediaTek XS-PHY driver
This patch series support the SuperSpeedPlus XS-PHY transceiver for
USB3.1 GEN2 controller on MediaTek chips. The dr
Support XS-PHY for MediaTek SoCs with USB3.1 GEN2 controller
Signed-off-by: Chunfeng Yun
---
drivers/phy/mediatek/Kconfig |9 +
drivers/phy/mediatek/Makefile|1 +
drivers/phy/mediatek/phy-mtk-xsphy.c | 600 ++
3 files changed, 610 insertio
In fact the driver depends on EXTCON only when it's configed as
USB_MTU3_DUAL_ROLE, so make USB_MTU3_DUAL_ROLE depend on EXTCON but
not USB_MTU3.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/mtu3/Kconfi
There is an error dialog popped up in PC when test TEST_J/K
by EHSETT tool, due to not waiting for the completion of
control transfer. Here fix it by entering test mode after
Status Stage finish.
Signed-off-by: Chunfeng Yun
---
v2:
1. reset test_mode as default value when controller is reset
The variable of 'count' is declared as u8, this will cause an issue
due to value truncated when works in SS or SSP mode and data length
is greater than 255, so change it as u32.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3_gadget_ep0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
Reset EP when disable it to reset data toggle for U2 EP, and
SeqN, flow control status etc for U3 EP, this can avoid
issue of uncontinuous SeqN
Signed-off-by: Chunfeng Yun
---
v2:
add this patch
---
drivers/usb/mtu3/mtu3_core.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/
The usb_add_gadget_udc() will set the gadget state as
USB_STATE_NOTATTACHED, so we needn't set it again.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3_gadget.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3_gadget.c b/drivers/usb/mtu3/mt
When boot on the platform with the USB cable connected to Win7,
the Win7 will pop up an error dialog: "USB Device not recognized",
but finally the Win7 can enumerate it successfully.
The root cause is as the following:
When the xHCI driver set PORT_POWER of the OTG port, and if both
IDPIN and VBUS_
After the controller receives a LPM request, it will reject the LPM
request, and need software to re-enable it after LPM resume if the
controller doesn't remote wakeup from L1 automatically
Signed-off-by: Chunfeng Yun
---
v2:
add this patch
---
drivers/usb/mtu3/mtu3_core.c | 8 +++-
1 fi
Hi, Greg
On Thu, 2018-05-10 at 10:16 +0800, Chunfeng Yun wrote:
> Hi, Greg
>
>Could you please pick up the series of patches, thanks a lot
Please ignore it, I find a problem in [RESEND PATCH 4/5], and need send
a new version.
Very sorry
>
> On Sat, 2018-05-05 at 10:21 +0800, Chunfeng Yun w
Hi, Greg
Could you please pick up the series of patches, thanks a lot
On Sat, 2018-05-05 at 10:21 +0800, Chunfeng Yun wrote:
> The variable of 'count' is declared as u8, this will cause an issue
> due to value truncated when works in SS or SSP mode and data length
> is greater than 255, so ch
On Tue, May 08, 2018 at 08:36:25AM -0700, James Bottomley wrote:
> Early boot means userspace. for a hot pluggable device, this would
> probably be something in udev if you follow the no-daemon model and the
> daemon could do it if you do follow the daemon model.
>
> James
Could this be implement
Hi,
On Wed, 2018-05-09 at 14:33 +0300, Felipe Balbi wrote:
> Hi,
>
> Chunfeng Yun writes:
> > The USB3CV version 2.1.80 (March 26, 2018) requires all devices
> > ( gen1, gen2, single lane, dual lane) to return the value of 0x0320
> > in the bcdUSB field
>
> this sounds really odd. What happens
On Tue, May 08, 2018 at 10:29:41AM -0500, David R. Bild wrote:
> On Tue, May 8, 2018 at 10:25 AM, James Bottomley
> wrote:
> >
> > > On Fri, May 04, 2018 at 02:56:25PM -0500, David R. Bild wrote:
> > [...]
> > > > In particular, it sets the credentials for the platform hierarchy.
> > > > The platf
On Tue, May 08, 2018 at 08:25:48AM -0700, James Bottomley wrote:
> On Tue, 2018-05-08 at 13:55 +0300, Jarkko Sakkinen wrote:
> > On Fri, May 04, 2018 at 02:56:25PM -0500, David R. Bild wrote:
> [...]
> > > In particular, it sets the credentials for the platform hierarchy.
> > > The platform hierarc
On Sun, May 06, 2018 at 09:02:29AM -0600, Jason Gunthorpe wrote:
> On Fri, May 04, 2018 at 03:19:21PM -0500, David R. Bild wrote:
> > Setting the platform hierarchy password to a random discarded value
> > (and the dictionary lockout reset) is really the only special work
> > done here. The other s
Hi
> -Original Message-
> From: Oliver Neukum [mailto:oneu...@suse.com]
> Sent: 2018年5月8日 18:03
> To: Jun Li ; robh...@kernel.org;
> heikki.kroge...@linux.intel.com; gre...@linuxfoundation.org;
> li...@roeck-us.net
> Cc: gso...@gmail.com; dl-linux-imx ; Peter Chen
> ; shufan_...@richtek.com
On Wed, 9 May 2018, Mauro Carvalho Chehab wrote:
> The script:
> ./scripts/documentation-file-ref-check --fix-rst
>
> Gives multiple hints for broken references on some files.
> Manually use the one that applies for some files.
>
> Signed-off-by: Mauro Carvalho Chehab
Acked-by: James Mo
Add separate dwc3-qcom glue driver for Qualcomm SOCs having dwc3 core.
It is needed to support peripheral mode.
Patches also add support to invoke PHY runtime PM functions on host
mode bus-suspend.
Changes since v3:
- Added SOC specific compatibles in driver.
Changes since v2:
- Addressed Rob's
Existing documentation has lot of incorrect information as it
was originally added for a driver that no longer exists.
Signed-off-by: Manu Gautam
Reviewed-by: Rob Herring
---
.../devicetree/bindings/usb/qcom,dwc3.txt | 85 --
1 file changed, 63 insertions(+), 22 del
Some PHY drivers (e.g. for Qualcomm QUSB2 and QMP PHYs) support
runtime PM to reduce PHY power consumption during bus_suspend.
Add changes to let core auto-suspend PHYs on host bus-suspend
using GUSB2PHYCFG register if needed for a platform. Also perform
PHYs runtime suspend/resume and let platform
DWC3 controller on Qualcomm SOCs has a Qscratch wrapper.
Some of its uses are described below resulting in need to
have a separate glue driver instead of using dwc3-of-simple:
- It exposes register interface to override vbus-override
and lane0-pwr-present signals going to hardware. These
mus
The script:
./scripts/documentation-file-ref-check --fix-rst
Gives multiple hints for broken references on some files.
Manually use the one that applies for some files.
Signed-off-by: Mauro Carvalho Chehab
---
Documentation/ABI/obsolete/sysfs-gpio | 2 +-
.../devicet
On Tue, May 08, 2018 at 09:10:13PM +0200, Mats Karrman wrote:
> Hi,
>
> On 05/08/2018 04:25 PM, Heikki Krogerus wrote:
>
> > Hi,
> >
> > On Mon, May 07, 2018 at 11:19:40PM +0200, Mats Karrman wrote:
> Even so, when the mux driver "set" function is called, it will just get
> the
>
The USB3CV version 2.1.80 (March 26, 2018) requires all devices
( gen1, gen2, single lane, dual lane) to return the value of 0x0320
in the bcdUSB field
Signed-off-by: Chunfeng Yun
---
drivers/usb/gadget/composite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/g
Hi,
Chunfeng Yun writes:
> The USB3CV version 2.1.80 (March 26, 2018) requires all devices
> ( gen1, gen2, single lane, dual lane) to return the value of 0x0320
> in the bcdUSB field
this sounds really odd. What happens when I get a USB 3.1 compliant
device off-the-shelf and run it through USB3
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb: dw
The commit 3bc04e28a030 ("usb: dwc2: host: Get aligned DMA in
a more supported way") rips out a lot of code to simply the
allocation of aligned DMA. However, it also introduces a new
issue when use isoc split in transfer.
In my test case, I connect the dwc2 controller with an usb hs
Hub (GL852G-12
If isoc split in transfer with no data (the length of DATA0
packet is zero), we can't simply return immediately. Because
the DATA0 can be the first transaction or the second transaction
for the isoc split in transaction. If the DATA0 packet with no
data is in the first transaction, we can return im
Dear Doug,
在 2018年05月08日 23:29, Doug Anderson 写道:
Hi,
On Tue, May 8, 2018 at 12:43 AM, wlf wrote:
Dear Doug,
在 2018年05月08日 13:11, Doug Anderson 写道:
Hi,
On Mon, May 7, 2018 at 8:07 PM, William Wu
wrote:
+static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
+
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