On Mon, May 09, 2016 at 12:45:38PM +0300, Roger Quadros wrote:
> On 06/05/16 12:41, Peter Chen wrote:
> > On Mon, May 02, 2016 at 03:18:46PM +0300, Roger Quadros wrote:
> >> The OTG core will use struct otg_hcd_ops to interface
> >> with the HCD controller.
> >>
> >> The main purpose of this interf
There is now a proper phy driver for the DA8xx SoC USB PHY. This adds the
platform device declarations needed to use it.
Signed-off-by: David Lechner
---
arch/arm/mach-davinci/board-da830-evm.c | 28 +---
arch/arm/mach-davinci/board-omapl138-hawk.c | 5 +
arch/ar
Up to this point, the USB phy clock configuration was handled manually in
the board files and in the usb drivers. This adds proper clocks so that
the usb drivers can use clk_get and clk_enable and not have to worry about
the details. Also, the related code is removed from the board files and
replac
Add a syscon node for the SoC CFGCHIPn registers. This is needed for
the new usb phy driver.
Signed-off-by: David Lechner
---
arch/arm/boot/dts/da850.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index cf1aad8..9546ace 10
The CFGCHIP registers are used by a number of devices, so using a syscon
device to share them. The first consumer of this will by the phy-da8xx-usb
driver.
Signed-off-by: David Lechner
---
arch/arm/mach-davinci/board-da830-evm.c | 4
arch/arm/mach-davinci/board-da850-evm.c | 4 +++
Add a node for the new usb phy driver.
Signed-off-by: David Lechner
---
arch/arm/boot/dts/da850.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 9546ace..b2ebbe5 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/ar
v5 changes: renamed "usbphy" to "usb_phy" or "usb-phy" as appropriate
David Lechner (5):
ARM: davinci: da8xx: add usb phy clocks
ARM: davinci: da8xx: Add CFGCHIP syscon platform declaration.
ARM: davinci: da8xx: Add USB PHY platform declaration
ARM: DTS: da850: Add cfgchip syscon node
AR
Device tree binding for new phy-da8xx-usb driver.
Signed-off-by: David Lechner
Acked-by: Rob Herring
---
.../devicetree/bindings/phy/phy-da8xx-usb.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
v5 changes:
Functionally, nothing has really changed. Just some cleanups based on feedback.
* Renamed "usbphy" to "usb_phy" or "usb-phy" as appropriate
* License header matches MODULE_LICENSE in new phy driver
David Lechner (7):
mfd: da8xx-cfgchip: New header file for CFGCHIP registers.
dt-b
We will be using a generic syscon device for the TI DA8XX SoC CFGCHIPx
retisters. This will be used by a number of planned drivers including a
new USB PHY driver and common clock framework drivers.
The same defines are removed from the platform_data header file since they
are now redundant and the
Simplify things a bit by using devm functions where possible.
Signed-off-by: David Lechner
---
drivers/usb/musb/da8xx.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index b03d3b8..0c1997c 100644
--- a
Including mach/* is frowned upon in device drivers, so get rid of it.
This replaces usb20_clk and code that pokes CFGCHIP2 with a proper phy
driver.
Signed-off-by: David Lechner
Acked-by: Alan Stern
---
drivers/usb/host/Kconfig | 1 +
drivers/usb/host/ohci-da8xx.c | 102
The initial use for this is for PHYs that have a mode related to USB OTG.
There are several SoCs (e.g. TI OMAP and DA8xx) that have a mode setting
in the USB PHY to override OTG VBUS and ID signals.
Of course, the enum can be expaned in the future to include modes for
other types of PHYs as well.
Use the new phy-da8xx-usb driver to take the place of the mach code that
pokes CFGCHIP2 in the da8xx musb glue driver. This unbreaks the driver.
Signed-off-by: David Lechner
---
drivers/usb/musb/Kconfig | 2 +-
drivers/usb/musb/da8xx.c | 135 ++-
2 f
This is a new phy driver for the SoC USB controllers on the TI DA8xx
family of microcontrollers. The USB 1.1 PHY is just a simple on/off.
The USB 2.0 PHY also allows overriding the VBUS and ID pins.
Signed-off-by: David Lechner
---
drivers/phy/Kconfig | 10 ++
drivers/phy/Makefile
On Mon, 2016-05-09 at 13:39 +0300, Felipe Balbi wrote:
> and patch all drivers similarly? Shouldn't arch/mips itself deal with
> it and hide it from drivers ?
Not sure what you mean, but we never had "endian neutral" accessors. It
would be a bit of an endeavour and we already have so many accessor
On Mon, 2016-05-09 at 17:08 +0200, Arnd Bergmann wrote:
>
> Unfortunately, I don't see any way this could be done in MIPS specific
> code: There is typically a byteswap between the internal bus and the PCI
> bus on big-endian MIPS systems, so the PCI MMIO ends up being little-endian,
Ugh ... not
On 05/04/2016 01:39 PM, Bin Liu wrote:
On Wed, May 04, 2016 at 01:20:36PM -0500, David Lechner wrote:
This is something I actually plan on using because the device I am
using (LEGO MINDSTORMS EV3) is not wired for OTG, so the callback is
needed to override the ID and VBUS signals when switching
On Mon, 2016-05-09 at 21:06 +0200, Christian Lamparter via Linuxppc-dev wrote:
>
> I ran into the following issues:
> - gadget.c uses ioread32_rep [0] & iowrite32_rep [1].
> This is interesting because both of these functions actually use
> the __raw_io* on powerpc. Thi
On Monday 09 May 2016 14:11:23 John Youn wrote:
> On 5/9/2016 1:39 PM, Arnd Bergmann wrote:
>
> > The systems are not a particular endianess, only the current state
> > of the CPU is, and that may change independent of the way the
> > hardware block got synthesized. We don't support swapping endian
On 5/9/2016 1:39 PM, Arnd Bergmann wrote:
> On Monday 09 May 2016 13:22:48 John Youn wrote:
>> On 5/9/2016 3:36 AM, Arnd Bergmann wrote:
>>> On Monday 09 May 2016 10:23:22 Benjamin Herrenschmidt wrote:
On Sun, 2016-05-08 at 13:44 +0200, Christian Lamparter wrote:
> On Sunday, May 08, 2016
On Monday 09 May 2016 13:22:48 John Youn wrote:
> On 5/9/2016 3:36 AM, Arnd Bergmann wrote:
> > On Monday 09 May 2016 10:23:22 Benjamin Herrenschmidt wrote:
> >> On Sun, 2016-05-08 at 13:44 +0200, Christian Lamparter wrote:
> >>> On Sunday, May 08, 2016 08:40:55 PM Benjamin Herrenschmidt wrote:
> >
On 5/9/2016 3:36 AM, Arnd Bergmann wrote:
> On Monday 09 May 2016 10:23:22 Benjamin Herrenschmidt wrote:
>> On Sun, 2016-05-08 at 13:44 +0200, Christian Lamparter wrote:
>>> On Sunday, May 08, 2016 08:40:55 PM Benjamin Herrenschmidt wrote:
On Sun, 2016-05-08 at 00:54 +0200, Christian Lamp
On Monday 09 May 2016 21:06:07 Christian Lamparter wrote:
> Uh, Thanks for the participation!
>
> On Monday, May 09, 2016 05:08:48 PM Arnd Bergmann wrote:
> > On Monday 09 May 2016 13:39:50 Felipe Balbi wrote:
> > > Arnd Bergmann writes:
> > > > On Monday 09 May 2016 10:23:22 Benjamin Herrenschmi
* Felipe Balbi [160505 23:49]:
>
> Hi,
>
> Bin Liu writes:
> >> Does the current 200 ms autosuspend timeout relate to anything real
> >> other than what I found out with my measurements?
> >
> > Not sure, I didn't checkk where the 200ms comes from.
>
> It was an arbitrary number from when runt
BTW, I have tested with two separate DA200 adapaters, they just behave
in the same unpredicatble way disconnecting and connecting from time to
time.
D.
On 09.05.2016 11:17, Greg KH wrote:
> On Mon, May 09, 2016 at 11:05:34AM +0200, Daniel Duris wrote:
>> Hi,
>>
>> this is an official DA200 Dell a
Hi William,
Did you leave off linux-rockc...@lists.infradead.org intentionally? IMO,
it's nice to have that list in CC, so interested parties can follow your
work, even if they aren't as fortunate as me to have been CC'd on your
patch directly.
On Mon, May 09, 2016 at 07:46:14PM +0800, William Wu
Uh, Thanks for the participation!
On Monday, May 09, 2016 05:08:48 PM Arnd Bergmann wrote:
> On Monday 09 May 2016 13:39:50 Felipe Balbi wrote:
> > Arnd Bergmann writes:
> > > On Monday 09 May 2016 10:23:22 Benjamin Herrenschmidt wrote:
> > >> On Sun, 2016-05-08 at 13:44 +0200, Christian Lamparte
On Mon, May 09, 2016 at 09:46:40AM +0200, Ulf Hansson wrote:
> On 6 May 2016 at 00:42, Rob Herring wrote:
> > On Thu, May 05, 2016 at 02:34:13PM +0200, Krzysztof Kozlowski wrote:
> >> Hi,
> >>
> >> This is a different, second try to fix usb3503+lan on Odroid U3 board
> >> if it was initialized by
Hi,
On Fri, May 06, 2016 at 10:41:46AM +, Andrew Goodbody wrote:
> > From: Bin Liu [mailto:b-...@ti.com]
> > On Thu, May 05, 2016 at 04:02:55PM +, Andrew Goodbody wrote:
> > > > From: Bin Liu [mailto:b-...@ti.com]
> > > > On Thu, May 05, 2016 at 03:12:00PM +, Andrew Goodbody wrote:
> >
> -Original Message-
> > From: Bin Liu [mailto:b-...@ti.com]
> > On Thu, May 05, 2016 at 04:02:55PM +, Andrew Goodbody wrote:
> > > > From: Bin Liu [mailto:b-...@ti.com] On Thu, May 05, 2016 at
> > > > 03:12:00PM +, Andrew Goodbody wrote:
> > > > > > From: Bin Liu [mailto:b-...@ti.c
William,
On Mon, May 9, 2016 at 4:46 AM, William Wu wrote:
> Signed-off-by: William Wu
> ---
> drivers/usb/dwc3/dwc3-of-simple.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-of-simple.c
> b/drivers/usb/dwc3/dwc3-of-simple.c
> index 9743353..1f3665b 100644
> --
On Monday 09 May 2016 13:39:50 Felipe Balbi wrote:
> Arnd Bergmann writes:
> > On Monday 09 May 2016 10:23:22 Benjamin Herrenschmidt wrote:
> >> On Sun, 2016-05-08 at 13:44 +0200, Christian Lamparter wrote:
> >
> > The patch that caused the problem had multiple issues:
> >
> > - it broke big-endia
On Friday 29 April 2016 18:13:30 Thierry Reding wrote:
> ARM: tegra: Enable the XUSB controller
>
> These changes add support for the XUSB controller on Tegra124. It is an
> XHCI compatible controller that replaces the existing EHCI controllers.
> Support is enabled on Venice2, Jetson TK1 and Nyan
On Thu, 05 May 2016, Lu Baolu wrote:
> Some Intel platforms have an USB port mux controlled by GPIOs.
> There's a single ACPI platform device that provides 1) USB ID
> extcon device; 2) USB vbus regulator device; and 3) USB port
> switch device. This MFD driver will split these 3 devices for
> the
On Friday 29 April 2016 17:52:28 Thierry Reding wrote:
> usb: host: xhci-tegra: Changes for v4.7-rc1
>
> This set of patches introduces a driver for the XUSB controller found on
> NVIDIA Tegra SoCs. When loaded with a firmware (available via the linux-
> firmware repository), it provides an XHCI-c
On Friday 29 April 2016 17:52:27 Thierry Reding wrote:
> PCI: tegra: Changes for v4.7-rc1
>
> These patches update the Tegra PCIe host bridge controller device tree
>
Merged into next/drivers, thanks!
Arnd
--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the bo
On Friday 29 April 2016 17:52:26 Thierry Reding wrote:
> phy: tegra: Changes for v4.7-rc1
>
> This set of patches adds support for the Tegra XUSB pad controller. The
> controller provides a set of pads (lanes) that are used for I/O by other
> IP blocks within Tegra SoCs (PCIe, SATA and XUSB).
>
>
On Mon, 2016-05-09 at 12:36 +0200, Arnd Bergmann wrote:
>
> I think we can simply make this set of accessors architecture-
> dependent
> (MIPS vs. the rest of the world) to revert ARM and PowerPC back to
> the working version.
Or use writel_be which mips seems to support...
Really, make it a BE
From: Sergei Shtylyov
Now that the DMA engine check was moved to musb_tx_dma_porgram(), both
musb_tx_dma_set_mode_cppi_tusb() and musb_tx_dma_set_mode_mentor() always
return 0, so we can make both these functions *void*.
Signed-off-by: Sergei Shtylyov
Signed-off-by: Bin Liu
---
drivers/usb/m
From: Sergei Shtylyov
Commit 754fe4a92c07 ("usb: musb: Remove ifdefs for TX DMA for musb_host.c")
looks incomplete: the DMA engine checks are done outside the Mentor/UX500
handler but inside the CPPI/TUSB handler. Move the checks out of the CPPI/
TUSB handler into its caller, musb_tx_dma_progra
urb->status is set when endpoint csr RXSTALL, H_ERROR, DATAERROR or
INCOMPRX bit is set. Those bits mean a broken pipe, so don't start next
urb when any of these bits is set by checking urb->status.
To minimize the risk of regression, only do so for RX, until we have a
test case to understand the
The MUSB Programming Guide states that the driver should clear RXCSR
bit2 when the controller sets the bit.
Signed-off-by: Bin Liu
---
drivers/usb/musb/musb_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 58487a4..90
Hi Greg,
Here are fixes for musb, which are ready to get into v4.7-rc1. Please let me
know if any change is needed.
Thanks,
-Bin.
Bin Liu (2):
usb: musb: host: clear rxcsr error bit if set
usb: musb: host: don't start next rx urb if current one failed
Sergei Shtylyov (2):
musb_host: move
William Wu writes:
> On 05/09/2016 08:10 PM, Felipe Balbi wrote:
>> William Wu writes:
> Thanks Felipe Balbi and Greg KH. I'm really sorry that I forgot to
> add changelog.
>>> Signed-off-by: William Wu
>> no changelog = no commit, sorry. Why do you want to dump GUCTL1?
> Because GUCT
Hi William,
William Wu writes:
> On 05/09/2016 08:18 PM, Felipe Balbi wrote:
>> Hi,
>>
>> William Wu writes:
>>> Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
>> this needs a quirk_ prefix...
> Yes, maybe a quirk is more proper. As you mentioned,
> the PHYIf can be confi
On 05/09/2016 08:18 PM, Felipe Balbi wrote:
Hi,
William Wu writes:
Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
this needs a quirk_ prefix...
Yes, maybe a quirk is more proper. As you mentioned,
the PHYIf can be configured during coreconsultant.
But for some speci
On 05/09/2016 08:10 PM, Felipe Balbi wrote:
William Wu writes:
Thanks Felipe Balbi and Greg KH. I'm really sorry that I forgot to
add changelog.
Signed-off-by: William Wu
no changelog = no commit, sorry. Why do you want to dump GUCTL1?
Because GUCTL1 can be written by user. For rock
Hi,
William Wu writes:
> Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
this needs a quirk_ prefix...
> interface is hardware property, and it's platform dependent,
> so we need to configure it in devicetree to set the core to
> support a UTMI+ PHY with an 8- or 16-bit interface.
>
William Wu writes:
> Signed-off-by: William Wu
no changelog = no commit, sorry. Why do you want to dump GUCTL1?
> ---
> drivers/usb/dwc3/core.h| 1 +
> drivers/usb/dwc3/debugfs.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>
On Mon, May 09, 2016 at 08:00:05PM +0800, William Wu wrote:
> Signed-off-by: William Wu
We can't take patches with no changelog text at all, sorry.
Please explain why you are doing what you are doing in the changelog
text.
thanks,
greg k-h
--
To unsubscribe from this list: send the line "unsub
Signed-off-by: William Wu
---
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e15e307..f268869 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -86,6 +86
Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
interface is hardware property, and it's platform dependent,
so we need to configure it in devicetree to set the core to
support a UTMI+ PHY with an 8- or 16-bit interface.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must set
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (4):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy interface configura
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu
---
Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
drivers/usb/dwc3/cor
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
drivers/usb/dwc3/core
Signed-off-by: William Wu
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c
b/drivers/usb/dwc3/dwc3-of-simple.c
index 9743353..1f3665b 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
Hi,
Arnd Bergmann writes:
> On Monday 09 May 2016 10:23:22 Benjamin Herrenschmidt wrote:
>> On Sun, 2016-05-08 at 13:44 +0200, Christian Lamparter wrote:
>> > On Sunday, May 08, 2016 08:40:55 PM Benjamin Herrenschmidt wrote:
>> > >
>> > > On Sun, 2016-05-08 at 00:54 +0200, Christian Lamparter v
On Monday 09 May 2016 10:23:22 Benjamin Herrenschmidt wrote:
> On Sun, 2016-05-08 at 13:44 +0200, Christian Lamparter wrote:
> > On Sunday, May 08, 2016 08:40:55 PM Benjamin Herrenschmidt wrote:
> > >
> > > On Sun, 2016-05-08 at 00:54 +0200, Christian Lamparter via Linuxppc-dev
> > > wrote:
> > >
On 06.05.2016 23:32, Joe Lawrence wrote:
Hello Mathias,
In c311e391a7ef "xhci: rework command timeout and cancellation," xHCI
command timeouts were refactored to flow through
xhci_handle_command_timeout. We've seen a few instances of
hangs/crashes with upstream and RHEL7.2 kernels where someone
Remove space before ',' and '(' .
This patch is detected by checkpatch.pl
Signed-off-by: Sandhya Bankar
---
drivers/usb/wusbcore/crypto.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/wusbcore/crypto.c b/drivers/usb/wusbcore/crypto.c
index f7fc2371..33acd15
Do not initialise statics to 0.
This patch is found by checkpatch.pl script.
Signed-off-by: Sandhya Bankar
---
drivers/usb/wusbcore/crypto.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/wusbcore/crypto.c b/drivers/usb/wusbcore/crypto.c
index 8ed8e34..f7fc2371 1
Hi,
Alan Stern writes:
> On Fri, 6 May 2016, Felipe Balbi wrote:
>
>> >> that's not a good idea, IMO. HCD drivers should be robust enough in
>> >> these situations.
>> >
>> > Why? Just so that hcd-tests.sh can complete with no errors? I don't
>>
>> and some off-the-shelf usb-network adapters
On 06/05/16 12:04, Peter Chen wrote:
> On Mon, May 02, 2016 at 03:18:54PM +0300, Roger Quadros wrote:
>> Now that we have a device reference in struct usb_otg
>> let's use dev_dbg() for debug messages.
>>
>> Signed-off-by: Roger Quadros
>> ---
>> drivers/usb/common/usb-otg-fsm.c | 19 +++-
On 06/05/16 12:41, Peter Chen wrote:
> On Mon, May 02, 2016 at 03:18:46PM +0300, Roger Quadros wrote:
>> The OTG core will use struct otg_hcd_ops to interface
>> with the HCD controller.
>>
>> The main purpose of this interface is to avoid directly
>> calling HCD APIs from the OTG core as they
>> w
Hey Greg,
thanks for the more info - I don't have a powered USB-C adapter/hub
available.
Where would I look for this autosuspend feature - in BIOS? I am using
KDE and as far as I know it does not have this setting.
Daniel
On 09.05.2016 11:17, Greg KH wrote:
> On Mon, May 09, 2016 at 11:05:34AM
On Mon, May 09, 2016 at 11:05:34AM +0200, Daniel Duris wrote:
> Hi,
>
> this is an official DA200 Dell adapter powered/connected via USB-C
> (adapter offers 4 ports: USB3, ETH, HDMI and VGA). I don't have any
> other with ETH port available to test.
If you plug it into a powered USB-C hub (yeah,
Hi,
this is an official DA200 Dell adapter powered/connected via USB-C
(adapter offers 4 ports: USB3, ETH, HDMI and VGA). I don't have any
other with ETH port available to test.
Daniel
On 09.05.2016 10:58, Greg KH wrote:
> On Mon, May 09, 2016 at 10:31:42AM +0200, Daniel Duris wrote:
>> 4.6.0-0
On Mon, May 09, 2016 at 10:31:42AM +0200, Daniel Duris wrote:
> 4.6.0-040600rc6-generic #201605012031
Ugh, that means you have the latest changes, so this really might be a
bad cable or power supply to the device.
If you use a "powered" hub, does that solve the issue?
thanks,
greg k-h
--
To uns
4.6.0-040600rc6-generic #201605012031
On 08.05.2016 18:14, Greg KH wrote:
> On Sun, May 08, 2016 at 02:54:29PM +0200, Daniel Duris wrote:
>> Every few seconds or minutes intermittent eth0 disconnection occurs (via USB
>> adapter DA200 on Dell XPS computer):
>>
>> [ 7745.623668] usb 4-1.4: usb_res
4.6.0-040600rc6-generic #201605012031
On 08.05.2016 18:14, Greg KH wrote:
> On Sun, May 08, 2016 at 02:54:29PM +0200, Daniel Duris wrote:
>> Every few seconds or minutes intermittent eth0 disconnection occurs (via USB
>> adapter DA200 on Dell XPS computer):
>>
>> [ 7745.623668] usb 4-1.4: usb_res
Heinrich Schuchardt writes:
> Remove redundant code.
> Or'ing with a shifted value of zero is a NOP.
>
> Signed-off-by: Heinrich Schuchardt
it sure is and the compiler is getting rid of those. They are there as
means of documentation only ;-)
I really have no strong feelings about this patch,
On 6 May 2016 at 00:42, Rob Herring wrote:
> On Thu, May 05, 2016 at 02:34:13PM +0200, Krzysztof Kozlowski wrote:
>> Hi,
>>
>> This is a different, second try to fix usb3503+lan on Odroid U3 board
>> if it was initialized by bootloader (e.g. for TFTP boot).
>>
>> First version:
>> http://www.spini
On Sun, May 08, 2016 at 08:09:53PM +0200, Johan Hovold wrote:
> On Sat, May 07, 2016 at 07:46:14PM +0200, Greg Kroah-Hartman wrote:
> > On Thu, May 05, 2016 at 12:13:11PM +0200, Johan Hovold wrote:
> > > Hi Greg,
> > >
> > > Here are some new modem device ids for the option driver. These have all
On 05/03/2016 04:33 PM, Florian Westphal wrote:
> Replace all trans_start updates with netif_trans_update helper.
> change was done via spatch:
>
> struct net_device *d;
> @@
> - d->trans_start = jiffies
> + netif_trans_update(d)
>
> Compile tested only.
>
> Cc: user-mode-linux-de...@lists.sourc
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