On Sun, Dec 6, 2015 at 4:39 AM, Finn Thain wrote:
>> - while (NCR5380_read(C400_CONTROL_STATUS_REG) &
>> CSR_HOST_BUF_NOT_RDY);
>> + while (NCR5380_read(hostdata->c400_ctl_status) &
>> CSR_HOST_BUF_NOT_RDY);
>
> The semicolon should appear on the next line where it is mor
Hi Finn,
On Sun, Dec 6, 2015 at 2:31 AM, Finn Thain wrote:
> When in process context, sleep during polling if doing so won't add
> significant latency. In interrupt context or if the lock is held, poll
> briefly then give up. Keep both core drivers in sync.
>
> Calibrate busy-wait iterations to a
Hi, I'm still having to have the following applied to be able to use the
eata driver for my DPT2044W SCSI card.
Is there any chance that this could be mainlined or another fix
implemented that can be mainlined?
As it is with the following patches applied, I still have to unload and
reload
On Sun, 6 Dec 2015, Geert Uytterhoeven wrote:
>
> As the caller of NCR5380_poll_politely() passes a timeout value in
> jiffies, calculations may become simpler if you store the number of
> accesses per jiffy instead of per ms.
Yes, I thought of that too. However, the number of accesses per ji
From: Colin Ian King
The max outstanding commands is being printed with a 0x prefix
to suggest it is a hex value, when in fact the integer decimal %d
format specifier is being used and this is a bit confusing. Use
%x instead to match the proceeding 0x prefix.
Signed-off-by: Colin Ian King
---
Convert compile-time C400_ register mapping to runtime mapping.
This removes the weird negative register offsets and allows adding
additional mappings.
While at it, convert read/write loops into insb/outsb.
Signed-off-by: Ondrej Zary
---
drivers/scsi/NCR5380.h | 13 +--
drivers/scsi/g_N
Add I/O register mapping for NCR53C400A and enable PDMA mode to
improve performance and fix non-working IRQ.
Tested with HP C2502 (and user-space enabler).
Signed-off-by: Ondrej Zary
---
drivers/scsi/g_NCR5380.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git
On Sunday 06 December 2015 04:40:56 Finn Thain wrote:
>
> On Fri, 4 Dec 2015, Ondrej Zary wrote:
>
> > Add I/O register mapping for DTC chips and enable PDMA mode.
> >
> > These chips have 16-bit wide HOST BUFFER register (counter register at
> > offset 0x0d increments by 2 on each HOST BUFFER r
Add I/O register mapping for DTC chips and enable PDMA mode.
These chips have 16-bit wide HOST BUFFER register and it must be read
by 16-bit accesses (we lose data otherwise).
Large PIO transfers crash at least the DTCT-436P chip (all reads result
in 0xFF) so this patch actually makes it work.
T
The check for 53C80 registers accessibility was commented out because
it was broken (inverted). Fix and enable it.
Signed-off-by: Ondrej Zary
---
drivers/scsi/g_NCR5380.c | 37 ++---
1 file changed, 6 insertions(+), 31 deletions(-)
diff --git a/drivers/scsi/g_N
Add I/O register mapping for DTC chips and enable PDMA mode.
These chips have 16-bit wide HOST BUFFER register and it must be read
by 16-bit accesses (we lose data otherwise).
Large PIO transfers crash at least the DTCT-436P chip (all reads result
in 0xFF) so this patch actually makes it work.
T
On Mon, 7 Dec 2015, Ondrej Zary wrote:
> The check for 53C80 registers accessibility was commented out because
> it was broken (inverted). Fix and enable it.
>
> Signed-off-by: Ondrej Zary
> ---
> drivers/scsi/g_NCR5380.c | 37 ++---
> 1 file changed, 6 insert
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