On Mon, Feb 08, 2016 at 03:36:52PM +, Joao Pinto wrote:
> Hi Mark,
>
> On 2/8/2016 3:30 PM, Mark Rutland wrote:
> > On Mon, Feb 08, 2016 at 03:17:11PM +, Joao Pinto wrote:
> >> Hi Mark and Arnd,
> >> Are you saying that a user that puts "snps,uf
On Mon, Feb 08, 2016 at 03:17:11PM +, Joao Pinto wrote:
> Hi Mark and Arnd,
>
> I am planning the v2 of this patch set. I have a doubt in the version
> compatibility strings... The core driver must support the UFS 2.0 controller
> and
> this patch set includes a patch that adds 2.0 capabiliti
On Wed, Feb 03, 2016 at 03:54:48PM +, Joao Pinto wrote:
> Hi,
>
> On 2/3/2016 3:39 PM, Arnd Bergmann wrote:
> > On Wednesday 03 February 2016 15:01:34 Joao Pinto wrote:
> >>
> >> Hi Arnd,
> >>
> >> On 2/3/2016 12:54 PM, Arnd Bergmann wrote:
> >>> On Wednesday 03 February 2016 11:28:26 Joao Pin
> + - ctrl-reg : offset to the following SAS control registers (in order):
> + - reset assert
> + - clock disable
> + - reset status
> + - reset de-assert
> + - clock enable
[...]
> >It would be better to have each offset in a separ
On Tue, Oct 27, 2015 at 01:09:15PM +, John Garry wrote:
> On 26/10/2015 14:45, Mark Rutland wrote:
> >On Mon, Oct 26, 2015 at 10:14:33PM +0800, John Garry wrote:
> >>Add devicetree bindings for HiSilicon SAS driver.
> >>
> >>Signed-off-by: John Garry
> &
> + sas_addr_prop = of_find_property(np, "sas-addr", NULL);
> + if (!sas_addr_prop || (sas_addr_prop->length != SAS_ADDR_SIZE))
> + goto err_out;
> + memcpy(hisi_hba->sas_addr, sas_addr_prop->value, SAS_ADDR_SIZE);
This was not in the binding.
What is this?
Thanks,
Mark.
On Mon, Oct 26, 2015 at 10:14:33PM +0800, John Garry wrote:
> Add devicetree bindings for HiSilicon SAS driver.
>
> Signed-off-by: John Garry
> ---
> .../devicetree/bindings/scsi/hisilicon-sas.txt | 70
> ++
> 1 file changed, 70 insertions(+)
> create mode 100644 Docume
On Wed, Apr 01, 2015 at 07:18:19PM +0100, Catalin Marinas wrote:
> On Wed, Apr 01, 2015 at 06:30:30PM +0100, Russell King - ARM Linux wrote:
> > On Wed, Apr 01, 2015 at 06:00:33PM +0100, Catalin Marinas wrote:
> > > The driver in general should not be ARM specific, though it runs on an
> > > ARMv8
On Wed, Apr 01, 2015 at 06:00:33PM +0100, Catalin Marinas wrote:
> On Wed, Apr 01, 2015 at 05:39:56PM +0100, Russell King - ARM Linux wrote:
> > On Wed, Apr 01, 2015 at 12:31:16PM -0400, Tejun Heo wrote:
> > > On Wed, Apr 01, 2015 at 12:13:36PM -0400, Tejun Heo wrote:
> > > > > Signed-off-by : Suma
On Wed, Jan 15, 2014 at 07:10:39AM +, Loc Ho wrote:
[...]
> + * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
> + * The first PLL clock macro is used for internal reference clock. The second
> + * PLL clock macro is used to generate the clock for the PHY. This driver
>
On Wed, Jan 15, 2014 at 07:10:38AM +, Loc Ho wrote:
> Signed-off-by: Loc Ho
> Signed-off-by: Tuan Phan
> Signed-off-by: Suman Tripathi
> ---
> .../devicetree/bindings/phy/apm-xgene-phy.txt | 94
>
> 1 files changed, 94 insertions(+), 0 deletions(-)
> create mod
On Wed, Jan 15, 2014 at 07:11:48AM +, Loc Ho wrote:
> Signed-off-by: Loc Ho
> Signed-off-by: Tuan Phan
> Signed-off-by: Suman Tripathi
> ---
> .../devicetree/bindings/ata/apm-xgene.txt | 68
>
> 1 files changed, 68 insertions(+), 0 deletions(-)
> create mod
On Tue, Nov 26, 2013 at 07:01:23AM +, Loc Ho wrote:
> Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS
> binding
>
> Signed-off-by: Loc Ho
> Signed-off-by: Tuan Phan
> Signed-off-by: Suman Tripathi
> ---
> .../devicetree/bindings/ata/apm-xgene.txt | 1
On Wed, Nov 20, 2013 at 08:07:45PM +, Loc Ho wrote:
> Hi,
>
> >> +- compatible : Shall be "apm,xgene-ahci-phy" or
> >> + "apm,xgene-ahci-phy2". The "apm,xgene-ahci-phy"
> >> + describes an port shared with SGMII Ethernet port.
> >> +
On Tue, Nov 19, 2013 at 11:53:17PM +, Loc Ho wrote:
> arm64: Add APM X-Gene SoC 6.0Gbps SATA PHY DTS entries
>
> This patch adds the DTS entries for the APM X-Gene SoC 6.0Gbps SATA PHY
> driver. The PHY for controller 0 and 1 are enabled by default.
>
> Signed-off-by: Loc Ho
> Signed-off-by:
Hi,
On Tue, Nov 19, 2013 at 11:53:16PM +, Loc Ho wrote:
> This patch adds support for APM X-Gene SoC 6.0Gbps SATA PHY. This is the
> physical layer interface for the corresponding SATA host controller. This
> driver uses the new PHY generic framework posted by Kishon Vijay Abrahm.
>
> Signed-
On Tue, Nov 19, 2013 at 11:53:15PM +, Loc Ho wrote:
> Documentation: Add APM X-Gene SoC 6.0Gbps SATA PHY driver binding
> documentation
>
> Document the DTS binding for the X-Gene SoC SATA PHY driver.
>
> Signed-off-by: Loc Ho
> Signed-off-by: Tuan Phan
> Signed-off-by: Suman Tripathi
> -
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