[PATCH 10/10] mpt3sas: Update driver version to 29.100.00.00

Update driver version from 28.100.00.00 to 29.100.00.00 This is equivalent to Phase 10 OOB driver. Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/m

[PATCH 09/10] mpt3sas: Introduce perf_mode module parameter

1. Introduce module parameter perf_mode for only Aero/Sea generation HBAs. 2. Update IOC page1 fields according to performance mode. Below are the performance modes that can be enabled with module parameter perf_mode. 0: Balanced - Few high iops reply queues will be enabled. Interrupt coale

[PATCH 08/10] mpt3sas: Enable interrupt coalescing on high iops

Enable interrupt coalescing only on high iops queues when high iops queues are enabled. In ioc config page 1, offset 0x14 (ProductSpecific field) is used to determine interrupt coalescing enabled/disabled on per reply descriptor post queue group(8) basis. If 31st bit is zero then interrupt coalesc

[PATCH 04/10] mpt3sas: change _base_get_msix_index prototype

Code refactoring. In function _base_get_msix_index add scmd as second argument. This change is required for creating function pointer in next patch, where we introduce new function to get the msix index for high iops queues Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c

[PATCH 05/10] mpt3sas: Use highiops queues if more in-flights

Driver will use round robin method for io submission in batches within the high iops queues when in-flight ios on the target device is more than 8. If in-flight ios per SCSI device more than 8, driver will use high iops queue else driver will use low latency reply queues. Signed-off-by: Suganath

[PATCH 06/10] mpt3sas: save msix index and use same while posting RD

Code refactor: In the IO submission path _base_get_msix_index is called twice, one while getting the smid; msix index is saved in msix_io filed in scsiio tracker and anther while posting the request descriptor(RD). now code refactor is done to determine msix index only while posting the request de

[PATCH 07/10] mpt3sas: Affinity high iops queues IRQs to local node

High iops queues are mapped to non-managed irqs. Set affinity of non-managed irqs to local numa node. Low latency queues are mapped to managed irq. Driver reserves some reply queues (pci_alloc_irq_vectors_affinity and .pre_vectors interface is used to meet the goal) for max iops and rest of queues

[PATCH 03/10] mpt3sas: Add flag high_iops_queues

Aero controllers supports balanced performance mode and driver enables set of high iops and low latency reply queue only if, - HBA is an AERO controller, - MSIXs vector supported by the HBA is 128, - Total CPU count in the system more than high iops queue count, - Loaded driver with default ma

[PATCH 02/10] mpt3sas: Add Atomic Request Descriptor support on Aero

If the Aero HBA supports Atomic Request Descriptors, it sets the Atomic Request Descriptor Capable bit in the IOCCapabilities field of the IOCFacts Reply message. Driver uses an Atomic Request Descriptor as an alternative method for posting an entry onto a request queue. The posting of an Atomic Re

[PATCH 01/10] mpt3sas: function pointers of request descriptor

This code refactoring introduces function pointers. Host uses Request Descriptors of different types for posting an entry onto a request queue. Based on controller type and capabilities, host can also use atomic descriptors other than normal descriptors. Using function pointer will avoid if-else s

[PATCH 00/10] mpt3sas: Aero/Sea HBA feature addition

In this patch series we are adding below two features for Aero/Sea HBA device. Aero/Sea series HBA is PCI4.0 based controllers. 1. Add Atomic Request descriptor support: Atomic Request Descriptor is an alternative method for posting an entry onto a request queue. The posting of an Atomic Request D

Re: Poor SWIOTLB Performance with HIGHMEM64G

On Thu, May 16, 2019 at 05:44:43PM -0400, tedheadster wrote: > On Thu, May 16, 2019 at 2:58 AM Christoph Hellwig wrote: > > > > Can you still send me the dmesg output with the AHCI debug patch? > > I'm curious why we can't do 64-bit DMA to your device. > > Christoph, > here is the dmesg output