In scsi core, __scsi_queue_insert should just put request back on
the queue and retry using the same command as before. However, for
blk-mq, scsi_mq_requeue_cmd is employed here which will unprepare
the request. To align with the semantics of __scsi_queue_insert,
use blk_mq_requeue_request with kic
Hi Bart
Thanks for your kindly response and directive.
On 03/03/2018 12:31 AM, Bart Van Assche wrote:
> On Fri, 2018-03-02 at 11:31 +0800, Jianchao Wang wrote:
>> diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c
>> index a86df9c..d2f1838 100644
>> --- a/drivers/scsi/scsi_lib.c
>> ++
On Fri, 2018-03-02 at 15:03 +, Don Brace wrote:
> > -Original Message-
> > From: Laurence Oberman [mailto:lober...@redhat.com]
> > Sent: Friday, March 02, 2018 8:09 AM
> > To: Ming Lei
> > Cc: Don Brace ; Jens Axboe > k>;
> > linux-bl...@vger.kernel.org; Christoph Hellwig ;
> > Mike
>
On Fri, 2018-03-02 at 11:31 +0800, Jianchao Wang wrote:
> diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c
> index a86df9c..d2f1838 100644
> --- a/drivers/scsi/scsi_lib.c
> +++ b/drivers/scsi/scsi_lib.c
> @@ -191,7 +191,13 @@ static void __scsi_queue_insert(struct scsi_cmnd *cmd,
> i
On 02/03/2018 15:57, Rob Herring wrote:
On Fri, Mar 2, 2018 at 9:06 AM, John Garry wrote:
> From: Xiaofei Tan
>
> For some new boards with hip07 chipset we are required to
> set PHY config registers differently. The hw property which
> determines how to set these registers is in the PHY signal
On Fri, Mar 2, 2018 at 9:06 AM, John Garry wrote:
> From: Xiaofei Tan
>
> For some new boards with hip07 chipset we are required to
> set PHY config registers differently. The hw property which
> determines how to set these registers is in the PHY signal
> attenuation readings.
>
> This patch add
From: Xiaofei Tan
In sysfs, there are two files about minimum linkrate, and also
two files for maximum linkrate. Take maximum linkrate example,
maximum_linkrate_hw is read-only and indicated by the register
HARD_PHY_LINKRATE, and maximum_linkrate is read-write and
corresponding to the register PR
From: Xiaofei Tan
It is an implicit regulation that error code that function returned
should be negative. But hisi_sas_task_prep() doesn't follow this.
This may cause problems in the upper layer code.
For example, in sas_expander.c of libsas, smp_execute_task_sg() may
return the number of bytes
From: Xiang Chen
The structure element hisi_sas_devices.running_req to count how
many commands are active is in effect only ever written in the
code, so remove it.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 -
drivers/scsi/hisi_sas/hisi_
From: Xiaofei Tan
For some new boards with hip07 chipset we are required to
set PHY config registers differently. The hw property which
determines how to set these registers is in the PHY signal
attenuation readings.
This patch add an devicetree property, hisi-signal-attenuation,
which is used t
From: Xiaofei Tan
The current 110ms expiry time is not long enough for the internal
abort task.
The reason is that the internal abort task could be blocked in HW
if the HW is retrying to set up link. The internal abort task will
be executed only when the retry process finished.
The maximum time
This patchset primarily adds support for the Huawei x6000 board,
which includes hip07 chipset. Unfortunately, due to some board
layout differences with our development board, we need to set
a PHY-related register differently for optimal signal quality. As
such, a signal attenuation property is adde
From: Xiang Chen
The patch does some code cleanup and fixes some small bugs:
- Correct return status of phy_up_v3_hw()
- Add static for function phy_get_max_linkrate_v3_hw()
- Change exception return status when no reset method
- Change magic value to ts->stat in slot_complete_vx_hw()
- Remove un
From: Xiaofei Tan
It is not right to set the register PROG_PHY_LINK_RATE while PHY
is still enabled. So if we want to change PHY linkrate, we need to
disable PHY before setting the register PROG_PHY_LINK_RATE, and then
start-up PHY. This patch is to fix this issue.
Signed-off-by: Xiaofei Tan
Si
From: Xiaofei Tan
The register SAS_PHY_CTRL is configured according to signal quality.
The signal quality is calculated by signal attenuation of hardware
physical link. It may be different for different PCB layout.
So, in order to give better support to new board, this patch add
support to readi
> -Original Message-
> From: Laurence Oberman [mailto:lober...@redhat.com]
> Sent: Friday, March 02, 2018 8:09 AM
> To: Ming Lei
> Cc: Don Brace ; Jens Axboe ;
> linux-bl...@vger.kernel.org; Christoph Hellwig ; Mike
> Snitzer ; linux-scsi@vger.kernel.org; Hannes Reinecke
> ; Arun Easi ; Om
On Fri, Mar 02, 2018 at 02:11:02PM +, Jeremy Cline wrote:
> Sure, I'll take care of it.
Thanks a lot.
Johannes
--
Johannes Thumshirn Storage
jthumsh...@suse.de+49 911 74053 689
SUSE LINUX GmbH, Maxfeldstr. 5, 904
On 03/02/2018 07:00 AM, Johannes Thumshirn wrote:
> On Thu, Mar 01, 2018 at 02:08:10PM +, Jeremy Cline wrote:
>> If the read-only flag is true on a SCSI disk, re-reading the partition
>> table sets the flag back to false.
>>
>> To observe this bug, you can run:
>>
>> 1. blockdev --setro /dev/sd
On Fri, 2018-03-02 at 10:16 +0800, Ming Lei wrote:
> On Thu, Mar 01, 2018 at 04:19:34PM -0500, Laurence Oberman wrote:
> > On Thu, 2018-03-01 at 14:01 -0500, Laurence Oberman wrote:
> > > On Thu, 2018-03-01 at 16:18 +, Don Brace wrote:
> > > > > -Original Message-
> > > > > From: Ming L
https://bugzilla.kernel.org/show_bug.cgi?id=198975
Bug ID: 198975
Summary: Highpoint 840A RocketRAID Controller and drives are
NOT detected by SCSI_HPTIOP kernel module
Product: SCSI Drivers
Version: 2.5
Kernel Version: 4.15.7
On Thu, Mar 01, 2018 at 02:08:10PM +, Jeremy Cline wrote:
> If the read-only flag is true on a SCSI disk, re-reading the partition
> table sets the flag back to false.
>
> To observe this bug, you can run:
>
> 1. blockdev --setro /dev/sda
> 2. blockdev --rereadpt /dev/sda
> 3. blockdev --getr
Hello Martin,
Thanks, and I promise to keep on working hard on not falling over my own feet
doing a git send-email!
Am 02.03.18 um 03:09 schrieb Martin K. Petersen:
Wilfried,
This patch fixes the byte order of the SGPIO api and brings it back in
sync with ledmon v0.80 and above.
The patch
On 01/03/2018 21:40, Rob Herring wrote:
On Tue, Feb 20, 2018 at 03:13:24AM +0800, John Garry wrote:
From: Xiaofei Tan
For some new boards with hip07 chipset we are required to
set PHY config registers differently. The hw property which
determines how to set these registers is in the PHY signal
From: Venkat Gopalakrishnan
Qcom ufs controller v3.1.0 supports 2 lanes, add support
to configure 2 lanes during phy initialization.
Signed-off-by: Venkat Gopalakrishnan
Signed-off-by: Subhash Jadavani
Signed-off-by: Can Guo
---
drivers/scsi/ufs/ufs-qcom.c | 20 +---
1 file c
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