Hi Jacopo,
On 8/21/19 4:24 PM, Jacopo Mondi wrote:
> Hello,
> +laura who has been working on supporting RAW capture for this
> driver.
>
> On Tue, Aug 20, 2019 at 12:13:12PM +0300, Sakari Ailus wrote:
>> Hi Hugues,
>>
>> On Tue, Jul 02, 2019 at 04:05:46PM +, Hugues FRUCHET wrote:
>>>
Hello,
+laura who has been working on supporting RAW capture for this
driver.
On Tue, Aug 20, 2019 at 12:13:12PM +0300, Sakari Ailus wrote:
> Hi Hugues,
>
> On Tue, Jul 02, 2019 at 04:05:46PM +, Hugues FRUCHET wrote:
> > Hi Sakari,
> >
> > On 6/27/19 6:05 PM, Sakari Ailus wrote:
> > > Hi
Hi Hugues,
On Tue, Jul 02, 2019 at 04:05:46PM +, Hugues FRUCHET wrote:
> Hi Sakari,
>
> On 6/27/19 6:05 PM, Sakari Ailus wrote:
> > Hi Hugues,
> >
> > On Thu, Jun 27, 2019 at 02:57:04PM +0200, Hugues Fruchet wrote:
> >> Add support of V4L2_CID_LINK_FREQ, this is needed
> >> by some CSI-2 rec
Hi Sakari,
On 6/27/19 6:05 PM, Sakari Ailus wrote:
> Hi Hugues,
>
> On Thu, Jun 27, 2019 at 02:57:04PM +0200, Hugues Fruchet wrote:
>> Add support of V4L2_CID_LINK_FREQ, this is needed
>> by some CSI-2 receivers.
>>
>> 384MHz is exposed for the time being, corresponding
>> to 96MHz pixel clock wi
Hi Hugues,
On Thu, Jun 27, 2019 at 02:57:04PM +0200, Hugues Fruchet wrote:
> Add support of V4L2_CID_LINK_FREQ, this is needed
> by some CSI-2 receivers.
>
> 384MHz is exposed for the time being, corresponding
> to 96MHz pixel clock with 2 bytes per pixel on 2 data lanes.
>
> This setup has been
