Hi,
On Thu, Jan 04, 2018 at 04:27:41PM +0100, Ondřej Jirman wrote:
> On Thu, Jan 04, 2018 at 03:06:25PM +0100, Maxime Ripard wrote:
> > On Mon, Dec 25, 2017 at 09:58:02AM +0100, Ondřej Jirman wrote:
> > > Hello,
> > >
> > > On Mon, Dec 25, 2017 at 11:15:26AM +0800, Yong wrote:
> > > > Hi,
> > > >
On Thu, Jan 04, 2018 at 03:06:25PM +0100, Maxime Ripard wrote:
> On Mon, Dec 25, 2017 at 09:58:02AM +0100, Ondřej Jirman wrote:
> > Hello,
> >
> > On Mon, Dec 25, 2017 at 11:15:26AM +0800, Yong wrote:
> > > Hi,
> > >
> > > On Fri, 22 Dec 2017 14:46:48 +0100
> > > Ondřej Jirman wrote:
> > >
> >
On Mon, Dec 25, 2017 at 09:58:02AM +0100, Ondřej Jirman wrote:
> Hello,
>
> On Mon, Dec 25, 2017 at 11:15:26AM +0800, Yong wrote:
> > Hi,
> >
> > On Fri, 22 Dec 2017 14:46:48 +0100
> > Ondřej Jirman wrote:
> >
> > > Hello,
> > >
> > > Yong Deng píše v Pá 22. 12. 2017 v 17:32 +0800:
> > > >
>
On Mon, Dec 25, 2017 at 11:15:26AM +0800, Yong wrote:
> Hi,
>
> On Fri, 22 Dec 2017 14:46:48 +0100
> Ondřej Jirman wrote:
>
> > Hello,
> >
> > Yong Deng píše v Pá 22. 12. 2017 v 17:32 +0800:
> > > This patchset add initial support for Allwinner V3s CSI.
> > >
> > > Allwinner V3s SoC have two C
On Mon, 25 Dec 2017 09:58:02 +0100
Ondřej Jirman wrote:
> Hello,
>
> On Mon, Dec 25, 2017 at 11:15:26AM +0800, Yong wrote:
> > Hi,
> >
> > On Fri, 22 Dec 2017 14:46:48 +0100
> > Ondřej Jirman wrote:
> >
> > > Hello,
> > >
> > > Yong Deng píše v Pá 22. 12. 2017 v 17:32 +0800:
> > > >
> > > >
Hello,
On Mon, Dec 25, 2017 at 11:15:26AM +0800, Yong wrote:
> Hi,
>
> On Fri, 22 Dec 2017 14:46:48 +0100
> Ondřej Jirman wrote:
>
> > Hello,
> >
> > Yong Deng píše v Pá 22. 12. 2017 v 17:32 +0800:
> > >
> > > Test input 0:
> > >
> > > Control ioctls:
> > > test VIDIO
Hi,
On Fri, 22 Dec 2017 14:46:48 +0100
Ondřej Jirman wrote:
> Hello,
>
> Yong Deng píše v Pá 22. 12. 2017 v 17:32 +0800:
> > This patchset add initial support for Allwinner V3s CSI.
> >
> > Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> > and CSI1 is used for parallel
Hello,
Yong Deng píše v Pá 22. 12. 2017 v 17:32 +0800:
> This patchset add initial support for Allwinner V3s CSI.
>
> Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> and CSI1 is used for parallel interface. This is not documented in
> datasheet but by testing and guess.
>