Hi Sam,
some comments and questions.
I still hope we find a way to merge our changes, but I need to
understand something before.
On Wed, Oct 17, 2018 at 10:31:48AM -0700, Sam Bobrowicz wrote:
> Remove the PLL settings from the register blobs and
> calculate them based on required clocks. This
Remove the PLL settings from the register blobs and
calculate them based on required clocks. This allows
more mode and input clock (xclk) configurations.
Also ensure that PCLK PERIOD register 0x4837 is set
so that MIPI receivers are not broken by this patch.
Last, a change to the init register bl
