On Fri, 22 Dec 2017 14:40:37 +0100
Philippe Ombredanne wrote:
> Yong,
>
> On Fri, Dec 22, 2017 at 11:21 AM, Priit Laes wrote:
> > On Fri, Dec 22, 2017 at 05:47:00PM +0800, Yong Deng wrote:
> >> Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> >> and CSI1 is used for para
Yong,
On Fri, Dec 22, 2017 at 11:21 AM, Priit Laes wrote:
> On Fri, Dec 22, 2017 at 05:47:00PM +0800, Yong Deng wrote:
>> Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
>> and CSI1 is used for parallel interface. This is not documented in
>> datasheet but by testing and gu
Hi,
On Fri, 22 Dec 2017 10:21:56 +
Priit Laes wrote:
> On Fri, Dec 22, 2017 at 05:47:00PM +0800, Yong Deng wrote:
> > Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> > and CSI1 is used for parallel interface. This is not documented in
> > datasheet but by testing and
On Fri, Dec 22, 2017 at 05:47:00PM +0800, Yong Deng wrote:
> Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> and CSI1 is used for parallel interface. This is not documented in
> datasheet but by testing and guess.
>
> This patch implement a v4l2 framework driver for it.
>
Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
and CSI1 is used for parallel interface. This is not documented in
datasheet but by testing and guess.
This patch implement a v4l2 framework driver for it.
Currently, the driver only support the parallel interface. MIPI-CSI2,
