RE: [PATCH v4 08/10] v4l: xilinx: Add Xilinx Video IP core

: Re: [PATCH v4 08/10] v4l: xilinx: Add Xilinx Video IP core > > On 01/22/15 04:01, Laurent Pinchart wrote: > > Hi Hans and Chris, > > > > On Monday 01 December 2014 22:13:38 Laurent Pinchart wrote: > >> Xilinx platforms have no hardwired video capture or video process

Re: [PATCH v4 08/10] v4l: xilinx: Add Xilinx Video IP core

On 01/22/15 04:01, Laurent Pinchart wrote: > Hi Hans and Chris, > > On Monday 01 December 2014 22:13:38 Laurent Pinchart wrote: >> Xilinx platforms have no hardwired video capture or video processing >> interface. Users create capture and memory to memory processing >> pipelines in the FPGA fabric

Re: [PATCH v4 08/10] v4l: xilinx: Add Xilinx Video IP core

Hi Hans and Chris, On Monday 01 December 2014 22:13:38 Laurent Pinchart wrote: > Xilinx platforms have no hardwired video capture or video processing > interface. Users create capture and memory to memory processing > pipelines in the FPGA fabric to suit their particular needs, by > instantiating

[PATCH v4 08/10] v4l: xilinx: Add Xilinx Video IP core

Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that model