On Tue, Sep 12, 2017 at 02:13:12PM -0500, Benoit Parrot wrote:
> > > + /*
> > > + * Create a static mapping between the CSI virtual channels
> > > + * and the output stream.
> > > + *
> > > + * This should be enhanced, but v4l2 lacks the support for
> > > + * changing that mapping dynamically.
Hi Benoit,
Thanks for your comments,
On Tue, Sep 12, 2017 at 01:23:39PM -0500, Benoit Parrot wrote:
> > +static int csi2rx_probe(struct platform_device *pdev)
> > +{
> > + struct v4l2_async_subdev **subdevs;
> > + struct csi2rx_priv *csi2rx;
> > + unsigned int i;
> > + int ret;
> > +
> >
Benoit Parrot wrote on Tue [2017-Sep-12 13:23:39 -0500]:
> > +static int csi2rx_start(struct csi2rx_priv *csi2rx)
> > +{
> > + unsigned int i;
> > + u32 reg;
> > + int ret;
> > +
> > + /*
> > +* We're not the first users, there's no need to enable the
> > +* whole controller.
>
Maxime,
Thanks for the patch.
Maxime Ripard wrote on Mon [2017-Sep-04
15:03:35 +0200]:
> The Cadence CSI-2 RX Controller is an hardware block meant to be used as a
> bridge between a CSI-2 bus and pixel grabbers.
>
> It supports operating with internal or external D-PHY, with up to 4 lanes,
>
The Cadence CSI-2 RX Controller is an hardware block meant to be used as a
bridge between a CSI-2 bus and pixel grabbers.
It supports operating with internal or external D-PHY, with up to 4 lanes,
or without any D-PHY. The current code only supports the former case.
It also support dynamic mappin
