On Thu, Oct 18, 2018 at 10:47:28AM +0200, jacopo mondi wrote:
> Hi Ettore,
>thanks for the patches.
>
> A few other things, please see below.
>
> On Wed, Oct 17, 2018 at 11:31:41PM +0200, ektor5 wrote:
> > From: Ettore Chimenti
> >
> > This patch adds support to the CEC device implemented wi
On 10/19/18 15:02, ektor5 wrote:
> Hi Hans,
>
> On Thu, Oct 18, 2018 at 09:14:55AM +0200, Hans Verkuil wrote:
>> Hi Ettore,
>>
>> Just a few small things and it is ready to go:
>>
>> On 10/17/2018 11:31 PM, ektor5 wrote:
>>> From: Ettore Chimenti
>>>
>>> This patch adds support to the CEC device
Hi Hans,
On Thu, Oct 18, 2018 at 09:14:55AM +0200, Hans Verkuil wrote:
> Hi Ettore,
>
> Just a few small things and it is ready to go:
>
> On 10/17/2018 11:31 PM, ektor5 wrote:
> > From: Ettore Chimenti
> >
> > This patch adds support to the CEC device implemented with a STM32
> > microcontrol
Hi Ettore,
thanks for the patches.
A few other things, please see below.
On Wed, Oct 17, 2018 at 11:31:41PM +0200, ektor5 wrote:
> From: Ettore Chimenti
>
> This patch adds support to the CEC device implemented with a STM32
> microcontroller in X86 SECO Boards, including UDOO X86.
>
> The com
Hi Ettore,
Just a few small things and it is ready to go:
On 10/17/2018 11:31 PM, ektor5 wrote:
> From: Ettore Chimenti
>
> This patch adds support to the CEC device implemented with a STM32
> microcontroller in X86 SECO Boards, including UDOO X86.
>
> The communication is achieved via Braswel
From: Ettore Chimenti
This patch adds support to the CEC device implemented with a STM32
microcontroller in X86 SECO Boards, including UDOO X86.
The communication is achieved via Braswell integrated SMBus
(i2c-i801). The driver use direct access to the PCI addresses, due to
the limitations of th
