Re: [PATCH net] selftests: virtio_net: add forgotten config options

On Wed, 19 Jun 2024 08:17:48 +0200, Jiri Pirko wrote: > From: Jiri Pirko > > One may use tools/testing/selftests/drivers/net/virtio_net/config > for example for vng build command like this one: > $ vng -v -b -f tools/testing/selftests/drivers/net/virtio_net/config > > In that case, the needed ker

Re: [PATCH net] selftests: virtio_net: add forgotten config options

On Wed, Jun 19, 2024 at 08:17:48AM +0200, Jiri Pirko wrote: > From: Jiri Pirko > > One may use tools/testing/selftests/drivers/net/virtio_net/config > for example for vng build command like this one: > $ vng -v -b -f tools/testing/selftests/drivers/net/virtio_net/config > > In that case, the nee

Re: [PATCH RFC 0/5] mm/gup: Introduce exclusive GUP pinning

Hi, On 19.06.24 04:44, John Hubbard wrote: On 6/18/24 5:05 PM, Elliot Berman wrote: In arm64 pKVM and QuIC's Gunyah protected VM model, we want to support grabbing shmem user pages instead of using KVM's guestmemfd. These hypervisors provide a different isolation model than the CoCo implementat

Re: [PATCH v4 00/14] security: digest_cache LSM

On Tue, 2024-06-18 at 19:20 -0400, Paul Moore wrote: > On Mon, Apr 15, 2024 at 10:25 AM Roberto Sassu > wrote: > > > > From: Roberto Sassu > > > > Integrity detection and protection has long been a desirable feature, to > > reach a large user base and mitigate the risk of flaws in the software

[PATCH v10 0/3] KVM: selftests: aarch64: Introduce pmu_event_filter_test

The test is inspired by the pmu_event_filter_test which implemented by x86. On the arm64 platform, there is the same ability to set the pmu_event_filter through the KVM_ARM_VCPU_PMU_V3_FILTER attribute. So add the test for arm64. The series first create the helper function which can be used for th

[PATCH v10 1/3] KVM: selftests: aarch64: Add helper function for the vpmu vcpu creation

Create a vcpu with vpmu would be a common requirement for the vpmu test, so add the helper function for the vpmu vcpu creation. And use those helper function in the vpmu_counter_access.c test. Use this chance to delete the meaningless ASSERT about the pmuver, because KVM does not advertise an IMP_

[PATCH v10 2/3] KVM: selftests: aarch64: Introduce pmu_event_filter_test

Introduce pmu_event_filter_test for arm64 platforms. The test configures PMUv3 for a vCPU, and sets different pmu event filters for the vCPU, and check if the guest can see those events which user allow and can't use those events which use deny. This test refactor the create_vpmu_vm() and make it

[PATCH v10 3/3] KVM: selftests: aarch64: Add invalid filter test in pmu_event_filter_test

Add the invalid filter test which sets the filter beyond the event space and sets the invalid action to double check if the KVM_ARM_VCPU_PMU_V3_FILTER will return the expected error. Reviewed-by: Raghavendra Rao Ananta Reviewed-by: Eric Auger Signed-off-by: Shaoqin Huang --- .../kvm/aarch64/pm

Re: [PATCH RFC 0/5] mm/gup: Introduce exclusive GUP pinning

Hi John and David, Thank you for your comments. On Wed, Jun 19, 2024 at 8:38 AM David Hildenbrand wrote: > > Hi, > > On 19.06.24 04:44, John Hubbard wrote: > > On 6/18/24 5:05 PM, Elliot Berman wrote: > >> In arm64 pKVM and QuIC's Gunyah protected VM model, we want to support > >> grabbing shmem

RE: [PATCH net] selftests: openvswitch: Use bash as interpreter

From: Simon Horman > Sent: 17 June 2024 11:34 ... > > sidenote: I like very much the idea to use the least powerful tool, like > > sh vs bash, awk vs gawk, but it breaks when we forget what is outside of > > the scope of the former/standard. > > Perhaps for shell, we could convert all the selftests

[PATCH v7 00/16] Add support for a few Zc* extensions, Zcmop and Zimop

Add support for (yet again) more RVA23U64 missing extensions. Add support for Zimop, Zcmop, Zca, Zcf, Zcd and Zcb extensions ISA string parsing, hwprobe and kvm support. Zce, Zcmt and Zcmp extensions have been left out since they target microcontrollers/embedded CPUs and are not needed by RVA23U64.

[PATCH v7 01/16] dt-bindings: riscv: add Zimop ISA extension description

Add description for the Zimop (May-Be-Operations) ISA extension which was ratified in commit 58220614a5f of the riscv-isa-manual. Signed-off-by: Clément Léger Reviewed-by: Charlie Jenkins --- Documentation/devicetree/bindings/riscv/extensions.yaml | 5 + 1 file changed, 5 insertions(+) dif

[PATCH v7 02/16] riscv: add ISA extension parsing for Zimop

Add parsing for Zimop ISA extension which was ratified in commit 58220614a5f of the riscv-isa-manual. Signed-off-by: Clément Léger Reviewed-by: Charlie Jenkins --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/ris

[PATCH v7 03/16] riscv: hwprobe: export Zimop ISA extension

Export Zimop ISA extension through hwprobe. Signed-off-by: Clément Léger Reviewed-by: Charlie Jenkins --- Documentation/arch/riscv/hwprobe.rst | 4 arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Docu

[PATCH v7 04/16] RISC-V: KVM: Allow Zimop extension for Guest/VM

Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zimop extension for Guest/VM. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files cha

[PATCH v7 05/16] KVM: riscv: selftests: Add Zimop extension to get-reg-list test

The KVM RISC-V allows Zimop extension for Guest/VM so add this extension to get-reg-list test. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 1 file changed, 4 insertions(+) diff --git a/tools/testing/se

[PATCH v7 06/16] dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description

Add description for Zca, Zcf, Zcd and Zcb extensions which are part the Zc* standard extensions for code size reduction. Additional validation rules are added since Zcb depends on Zca, Zcf, depends on Zca and F, Zcd depends on Zca and D and finally, Zcf can not be present on rv64. Signed-off-by: C

[PATCH v7 07/16] riscv: add ISA extensions validation callback

Since a few extensions (Zicbom/Zicboz) already needs validation and future ones will need it as well (Zc*) add a validate() callback to struct riscv_isa_ext_data. This require to rework the way extensions are parsed and split it in two phases. First phase is isa string or isa extension list parsing

[PATCH v7 08/16] riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb

The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors. Signed-off-by: Clément Léger Review

[PATCH v7 09/16] riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions

Export Zca, Zcf, Zcd and Zcb ISA extension through hwprobe. Signed-off-by: Clément Léger Reviewed-by: Charlie Jenkins --- Documentation/arch/riscv/hwprobe.rst | 20 arch/riscv/include/uapi/asm/hwprobe.h | 4 arch/riscv/kernel/sys_hwprobe.c | 4 3 files ch

[PATCH v7 10/16] RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM

Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zca, Zcf, Zcd and Zcb extensions for Guest/VM. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 4 arch/riscv/kvm/vcpu_onereg.c

[PATCH v7 11/16] KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test

The KVM RISC-V allows Zca, Zcf, Zcd and Zcb extensions for Guest/VM so add these extensions to get-reg-list test. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 16 1 file changed, 16 insertions(

[PATCH v7 12/16] dt-bindings: riscv: add Zcmop ISA extension description

Add description for the Zcmop (Compressed May-Be-Operations) ISA extension which was ratified in commit c732a4f39a4c ("Zcmop is ratified/1.0") of the riscv-isa-manual. Signed-off-by: Clément Léger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml| 12

[PATCH v7 13/16] riscv: add ISA extension parsing for Zcmop

Add parsing for Zcmop ISA extension which was ratified in commit c732a4f39a4c ("Zcmop is ratified/1.0") of the riscv-isa-manual. Signed-off-by: Clément Léger Reviewed-by: Conor Dooley Reviewed-by: Charlie Jenkins --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2

[PATCH v7 14/16] riscv: hwprobe: export Zcmop ISA extension

Export Zcmop ISA extension through hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 4 arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.r

[PATCH v7 15/16] RISC-V: KVM: Allow Zcmop extension for Guest/VM

Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zcmop extension for Guest/VM. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files cha

[PATCH v7 16/16] KVM: riscv: selftests: Add Zcmop extension to get-reg-list test

The KVM RISC-V allows Zcmop extension for Guest/VM so add this extension to get-reg-list test. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 1 file changed, 4 insertions(+) diff --git a/tools/testing/se

Re: [PATCH RFC 0/5] mm/gup: Introduce exclusive GUP pinning

On Wed, Jun 19, 2024 at 10:11:35AM +0100, Fuad Tabba wrote: > To be honest, personally (speaking only for myself, not necessarily > for Elliot and not for anyone else in the pKVM team), I still would > prefer to use guest_memfd(). I think that having one solution for > confidential computing that

Re: [PATCH RFC 0/5] mm/gup: Introduce exclusive GUP pinning

Hi Jason, On Wed, Jun 19, 2024 at 12:51 PM Jason Gunthorpe wrote: > > On Wed, Jun 19, 2024 at 10:11:35AM +0100, Fuad Tabba wrote: > > > To be honest, personally (speaking only for myself, not necessarily > > for Elliot and not for anyone else in the pKVM team), I still would > > prefer to use gue

Re: [PATCH RFC 0/5] mm/gup: Introduce exclusive GUP pinning

On 19.06.24 11:11, Fuad Tabba wrote: Hi John and David, Thank you for your comments. On Wed, Jun 19, 2024 at 8:38 AM David Hildenbrand wrote: Hi, On 19.06.24 04:44, John Hubbard wrote: On 6/18/24 5:05 PM, Elliot Berman wrote: In arm64 pKVM and QuIC's Gunyah protected VM model, we want to

Re: [PATCH RFC 0/5] mm/gup: Introduce exclusive GUP pinning

If the memory can't be accessed by the CPU then it shouldn't be mapped into a PTE in the first place. The fact you made userspace faults (only) work is nifty but still an ugly hack to get around the fact you shouldn't be mapping in the first place. We already have ZONE_DEVICE/DEVICE_PRIVATE to ha

Re: [PATCH v2] selftests: openvswitch: Set value to nla flags.

Hello: This patch was applied to netdev/net.git (main) by David S. Miller : On Tue, 18 Jun 2024 09:29:21 +0200 you wrote: > Netlink flags, although they don't have payload at the netlink level, > are represented as having "True" as value in pyroute2. > > Without it, trying to add a flow with a f

Re: [PATCH RFC 0/5] mm/gup: Introduce exclusive GUP pinning

On Wed, Jun 19, 2024 at 01:01:14PM +0100, Fuad Tabba wrote: > Hi Jason, > > On Wed, Jun 19, 2024 at 12:51 PM Jason Gunthorpe wrote: > > > > On Wed, Jun 19, 2024 at 10:11:35AM +0100, Fuad Tabba wrote: > > > > > To be honest, personally (speaking only for myself, not necessarily > > > for Elliot an

[PATCH 0/5] riscv: add support for Zaamo and Zalrsc extensions

Since commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"), the A extension has been described as a set of instructions provided by Zaamo and Zalrsc. Add these two extensions. This series is based on the Zc one [1]. Link: https://lore.kernel.org/linux-riscv/20240619113529.676940-1-cle

[PATCH 1/5] dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description

Add description for the Zaamo and Zalrsc ISA extension[1]. Link: https://github.com/riscv/riscv-zaamo-zalrsc [1] Signed-off-by: Clément Léger --- .../devicetree/bindings/riscv/extensions.yaml | 19 +++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindin

[PATCH 2/5] riscv: add parsing for Zaamo and Zalrsc extensions

These 2 new extensions are actually a subset of the A extension which provides atomic memory operations and load-reserved/store-conditional instructions. Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 9 - 2 files changed, 10 inse

[PATCH 3/5] riscv: hwprobe: export Zaamo and Zalrsc extensions

Export the Zaamo and Zalrsc extensions to userspace using hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 8 arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/Docu

[PATCH 4/5] RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM

Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zaamo/Zalrsc extensions for Guest/VM. Signed-off-by: Clément Léger --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu_onereg.c | 4 2 files changed, 6 insertions(+) diff --git a/

[PATCH 5/5] KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test

The KVM RISC-V allows Zaamo/Zalrsc extensions for Guest/VM so add these extensions to get-reg-list test. Signed-off-by: Clément Léger --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 1 file changed, 8 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c

Re: [PATCH v4 00/14] security: digest_cache LSM

On Wed, Jun 19, 2024 at 3:59 AM Roberto Sassu wrote: > On Tue, 2024-06-18 at 19:20 -0400, Paul Moore wrote: > > On Mon, Apr 15, 2024 at 10:25 AM Roberto Sassu > > wrote: > > > > > > From: Roberto Sassu > > > > > > Integrity detection and protection has long been a desirable feature, to > > > rea

Re: [PATCH v4 00/14] security: digest_cache LSM

On Wed, 2024-06-19 at 11:49 -0400, Paul Moore wrote: > On Wed, Jun 19, 2024 at 3:59 AM Roberto Sassu > wrote: > > On Tue, 2024-06-18 at 19:20 -0400, Paul Moore wrote: > > > On Mon, Apr 15, 2024 at 10:25 AM Roberto Sassu > > > wrote: > > > > > > > > From: Roberto Sassu > > > > > > > > Integrity

RE: Testing Quality Call notes - 2024-06-13

Hi Tim, On 6/18/24 19:29, Bird, Tim wrote: >> -Original Message- >> From: Laura Nao >> >> KernelCI is hosting a bi-weekly call on Thursday to discuss improvements >> to existing upstream tests, the development of new tests to increase >> kernel testing coverage, and the enablement of thes

Re: [PATCH v4 00/14] security: digest_cache LSM

On Wed, Jun 19, 2024 at 11:55 AM Roberto Sassu wrote: > On Wed, 2024-06-19 at 11:49 -0400, Paul Moore wrote: > > On Wed, Jun 19, 2024 at 3:59 AM Roberto Sassu > > wrote: > > > On Tue, 2024-06-18 at 19:20 -0400, Paul Moore wrote: > > > > On Mon, Apr 15, 2024 at 10:25 AM Roberto Sassu > > > > wrot

Re: [PATCH v4 00/14] security: digest_cache LSM

On Wed, 2024-06-19 at 12:34 -0400, Paul Moore wrote: > On Wed, Jun 19, 2024 at 11:55 AM Roberto Sassu > wrote: > > On Wed, 2024-06-19 at 11:49 -0400, Paul Moore wrote: > > > On Wed, Jun 19, 2024 at 3:59 AM Roberto Sassu > > > wrote: > > > > On Tue, 2024-06-18 at 19:20 -0400, Paul Moore wrote: > >

Re: [PATCH v3 5/5] KVM: selftests: KVM: SVM: Add Idle HLT intercept test

Hi Chao, Thanks for reviewing the patches. On 5/31/2024 12:19 PM, Chao Gao wrote: > On Thu, May 30, 2024 at 06:49:56PM +0530, Manali Shukla wrote: >> Hi Chao, >> Thank you for reviewing my patches. >> >> On 5/28/2024 1:16 PM, Chao Gao wrote: +static void guest_code(void) +{ + uint

Re: [PATCH 2/5] riscv: add parsing for Zaamo and Zalrsc extensions

On Wed, Jun 19, 2024 at 05:39:09PM +0200, Clément Léger wrote: > These 2 new extensions are actually a subset of the A extension which > provides atomic memory operations and load-reserved/store-conditional > instructions. I wish this silly degree of fragmentation didn't exist. Acked-by: Conor Do

Re: [PATCH 1/5] dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description

On Wed, Jun 19, 2024 at 05:39:08PM +0200, Clément Léger wrote: > Add description for the Zaamo and Zalrsc ISA extension[1]. > > Link: https://github.com/riscv/riscv-zaamo-zalrsc [1] > Signed-off-by: Clément Léger Acked-by: Conor Dooley signature.asc Description: PGP signature

Re: [PATCH-cgroup v2 0/5] cgroup/cpuset: Fix miscellaneous issues

On Mon, Jun 17, 2024 at 10:39:40AM -0400, Waiman Long wrote: > v2: > - Fix test_cpuset_prs.sh problems reported by test robot > - Relax restriction imposed between cpuset.cpus.exclusive and > cpuset.cpus of sibling cpusets. > - Make cpuset.cpus.exclusive independent of cpuset.cpus. >

Re: [PATCH v2 3/5] kunit: string-stream-test: Make it a separate module

On 6/18/24 10:03, Ivan Orlov wrote: Currently, the only way to build string-stream-test is by setting CONFIG_KUNIT_TEST=y. However, CONFIG_KUNIT_TEST is a config option for a different test (`kunit-test.c`). Introduce a new Kconfig entry in order to be able to build the string-stream-test test a

Re: [PATCH v3 2/2] usercopy: Convert test_user_copy to KUnit test

On 6/12/24 12:59, Kees Cook wrote: Convert the runtime tests of hardened usercopy to standard KUnit tests. Additionally disable usercopy_test_invalid() for systems with separate address spaces (or no MMU) since it's not sensible to test for address confusion there (e.g. m68k). Co-developed-by:

Re: [PATCH v4 00/14] security: digest_cache LSM

On Wed, Jun 19, 2024 at 12:38 PM Roberto Sassu wrote: > > Making it a kernel subsystem would likely mean replicating what the LSM > infrastructure is doing, inode (security) blob and being notified about > file/directory changes. Just because the LSM framework can be used for something, perhaps i

[PATCH v2] kunit/usercopy: Disable testing on !CONFIG_MMU

Since arch_pick_mmap_layout() is an inline for non-MMU systems, disable this test there. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202406160505.ubge6tmy-...@intel.com/ Signed-off-by: Kees Cook --- Resending as v2 with Shuah in To: --- Cc: Shuah Khan Cc: Brend

[PATCH] kunit/usercopy: Add missing MODULE_DESCRIPTION()

From: Jeff Johnson Fix warning seen with: $ make allmodconfig && make W=1 C=1 lib/usercopy_kunit.ko WARNING: modpost: missing MODULE_DESCRIPTION() in lib/usercopy_kunit.o Signed-off-by: Jeff Johnson Signed-off-by: Kees Cook --- At Jeff's reminder, I've split this out of: https://lore.kernel.o

Re: [PATCH v3 2/2] usercopy: Convert test_user_copy to KUnit test

On Wed, Jun 19, 2024 at 11:38:31AM -0700, Jeff Johnson wrote: > On 6/12/24 12:59, Kees Cook wrote: > > Convert the runtime tests of hardened usercopy to standard KUnit tests. > > > > Additionally disable usercopy_test_invalid() for systems with separate > > address spaces (or no MMU) since it's no

[PATCH net-next v3 00/10] net: openvswitch: Add sample multicasting.

** Background ** Currently, OVS supports several packet sampling mechanisms (sFlow, per-bridge IPFIX, per-flow IPFIX). These end up being translated into a userspace action that needs to be handled by ovs-vswitchd's handler threads only to be forwarded to some third party application that will some

[PATCH net-next v3 07/10] selftests: openvswitch: add emit_sample action

Add sample and emit_sample action support to ovs-dpctl.py. Refactor common attribute parsing logic into an external function. Signed-off-by: Adrian Moreno --- .../selftests/net/openvswitch/ovs-dpctl.py| 162 +- 1 file changed, 161 insertions(+), 1 deletion(-) diff --git a/t

[PATCH net-next v3 08/10] selftests: openvswitch: add userspace parsing

The userspace action lacks parsing support plus it contains a bug in the name of one of its attributes. This patch makes userspace action work. Signed-off-by: Adrian Moreno --- .../selftests/net/openvswitch/ovs-dpctl.py| 24 +-- 1 file changed, 22 insertions(+), 2 deletions(

[PATCH net-next v3 09/10] selftests: openvswitch: parse trunc action

The trunc action was supported decode-able but not parse-able. Add support for parsing the action string. Signed-off-by: Adrian Moreno --- .../testing/selftests/net/openvswitch/ovs-dpctl.py | 13 + 1 file changed, 13 insertions(+) diff --git a/tools/testing/selftests/net/openvswitc

[PATCH net-next v3 10/10] selftests: openvswitch: add emit_sample test

Add a test to verify sampling packets via psample works. In order to do that, create a subcommand in ovs-dpctl.py to listen to on the psample multicast group and print samples. Signed-off-by: Adrian Moreno --- .../selftests/net/openvswitch/openvswitch.sh | 110 +- .../selftests

[PATCH] kselftest: dt: Ignore nodes that have ancestors disabled

echo "${node}" | grep -q -E "${disabled_nodes_regex}" && continue + fi + echo "${node}" | sed -e 's|\/proc\/device-tree||' done | sort ) --- base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0 change-id: 20240619-dt-kselftest-parent-disabled-2282a7223d26 Best regards, -- Nícolas F. R. A. Prado

[PATCH V4] rcutorture: Add CFcommon.arch for the various arch's need

Add CFcommon.arch for the various arch's need for rcutorture. In accordance with [1], [2] and [3], move x86 specific kernel option CONFIG_HYPERVISOR_GUEST to CFcommon.arch, also move kernel option CONFIG_KVM_GUEST which only exists on x86 & PowerPC to CFcommon.arch. [1] https://lore.kern

[PATCH v3 00/13] riscv: Add support for xtheadvector

xtheadvector is a custom extension that is based upon riscv vector version 0.7.1 [1]. All of the vector routines have been modified to support this alternative vector version based upon whether xtheadvector was determined to be supported at boot. vlenb is not supported on the existing xtheadvector

[PATCH v3 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description

The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins Reviewed-by: Conor Doole

[PATCH v3 02/13] dt-bindings: cpus: add a thead vlen register length property

Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, rea

[PATCH v3 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree

The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/ris

[PATCH v3 04/13] riscv: Add thead and xtheadvector as a vendor extension

Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.vendor| 13 + arch/riscv/include/asm/vendor_extensions/thead.h | 16 ++

[PATCH v3 05/13] riscv: vector: Use vlenb from DT for thead

If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.vendor | 13 ++ arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/kernel/cpufeature.c | 48 +++

[PATCH v3 06/13] RISC-V: define the elements of the VCSR vector CSR

From: Heiko Stuebner The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 5

[PATCH v3 07/13] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT

The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/include/a

[PATCH v3 09/13] riscv: vector: Support xtheadvector save/restore

Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/include/asm/csr.h | 6 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h| 249 +

[PATCH v3 10/13] riscv: hwprobe: Add thead vendor extension probing

Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RI

[PATCH v3 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension

Document support for thead vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 10 ++ 1 file

[PATCH v3 12/13] selftests: riscv: Fix vector tests

Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases is vector is reported and properly report the test case as skipped otherwise. The v_ini

[PATCH v3 13/13] selftests: riscv: Support xtheadvector in vector tests

Extend existing vector tests to be compatible with the xtheadvector instructions. Signed-off-by: Charlie Jenkins --- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 23 -- tools/testing/selftests/riscv/vector/v_helpers.c | 17 +++- tools/testing/selftests/riscv/vector/v_helpers.h |

[PATCH] selftests/mm: Introduce a test program to assess swap entry allocation for thp_swapout

From: Barry Song Both Ryan and Chris have been utilizing the small test program to aid in debugging and identifying issues with swap entry allocation. While a real or intricate workload might be more suitable for assessing the correctness and effectiveness of the swap allocation policy, a small t

Re: [RFC PATCH 1/2] riscv: Expose orig_a0 in the user_regs_struct structure

On Wed, Jun 19, 2024 at 10:01:27AM +0800, zhouq...@iscas.ac.cn wrote: > From: Quan Zhou > > Expose orig_a0 to userspace to ensure that users can modify > the actual value of `a0` in the traced process through the > ptrace(PTRACE_SETREGSET, ...) path. Since user_regs_struct is > a subset of pt_reg

Re: [PATCH] selftests/mm: Introduce a test program to assess swap entry allocation for thp_swapout

Barry Song <21cn...@gmail.com> writes: > From: Barry Song > > Both Ryan and Chris have been utilizing the small test program to aid > in debugging and identifying issues with swap entry allocation. While > a real or intricate workload might be more suitable for assessing the > correctness and eff

Re: [PATCH] selftests/mm: Introduce a test program to assess swap entry allocation for thp_swapout

On Thu, Jun 20, 2024 at 1:55 PM Huang, Ying wrote: > > Barry Song <21cn...@gmail.com> writes: > > > From: Barry Song > > > > Both Ryan and Chris have been utilizing the small test program to aid > > in debugging and identifying issues with swap entry allocation. While > > a real or intricate work

Re: [RFC PATCH 1/2] riscv: Expose orig_a0 in the user_regs_struct structure

On 2024/6/20 09:05, Charlie Jenkins wrote: On Wed, Jun 19, 2024 at 10:01:27AM +0800, zhouq...@iscas.ac.cn wrote: From: Quan Zhou Expose orig_a0 to userspace to ensure that users can modify the actual value of `a0` in the traced process through the ptrace(PTRACE_SETREGSET, ...) path. Since us

Re: [RFC PATCH 2/2] riscv: selftests: Add a ptrace test to check a0 of restarted syscall

On Wed, Jun 19, 2024 at 10:01:47AM +0800, zhouq...@iscas.ac.cn wrote: > From: Quan Zhou > > This test creates two processes: a tracer and a tracee. The tracer actively > sends a SIGUSR1 signal in user mode to interrupt the read syscall being > executed by the tracee. We will reset a0/orig_a0 and

Re: [PATCH RFC 0/5] mm/gup: Introduce exclusive GUP pinning

On Wed, Jun 19, 2024 at 08:51:35AM -0300, Jason Gunthorpe wrote: > If you can't agree with the guest_memfd people on how to get there > then maybe you need a guest_memfd2 for this slightly different special > stuff instead of intruding on the core mm so much. (though that would > be sad) Or we're

Re: [PATCH] selftests/mm: Introduce a test program to assess swap entry allocation for thp_swapout

Barry Song <21cn...@gmail.com> writes: > On Thu, Jun 20, 2024 at 1:55 PM Huang, Ying wrote: >> >> Barry Song <21cn...@gmail.com> writes: >> >> > From: Barry Song >> > >> > Both Ryan and Chris have been utilizing the small test program to aid >> > in debugging and identifying issues with swap ent

Re: [PATCH] selftests/mm: Introduce a test program to assess swap entry allocation for thp_swapout

On Thu, Jun 20, 2024 at 5:22 PM Huang, Ying wrote: > > Barry Song <21cn...@gmail.com> writes: > > > On Thu, Jun 20, 2024 at 1:55 PM Huang, Ying wrote: > >> > >> Barry Song <21cn...@gmail.com> writes: > >> > >> > From: Barry Song > >> > > >> > Both Ryan and Chris have been utilizing the small tes

Re: [PATCH] selftests/mm: Introduce a test program to assess swap entry allocation for thp_swapout

Barry Song <21cn...@gmail.com> writes: > On Thu, Jun 20, 2024 at 5:22 PM Huang, Ying wrote: >> >> Barry Song <21cn...@gmail.com> writes: >> >> > On Thu, Jun 20, 2024 at 1:55 PM Huang, Ying wrote: >> >> >> >> Barry Song <21cn...@gmail.com> writes: >> >> >> >> > From: Barry Song >> >> > >> >> > B