On Mon, 12 May 2025 12:41:09 +0100, Ben Horgan wrote:
> The ID_AA64PFR1_EL1.MTE_frac field is currently hidden from KVM.
> However, when ID_AA64PFR1_EL1.MTE==2, ID_AA64PFR1_EL1.MTE_frac==0
> indicates that MTE_ASYNC is supported. On a host with
> ID_AA64PFR1_EL1.MTE==2 but without MTE_ASYNC support
On Mon, 14 Apr 2025 13:40:58 +0100,
Ben Horgan wrote:
>
> If MTE_frac is masked out unconditionally then the guest will always
> see ID_AA64PFR1_EL1_MTE_frac as 0. However, a value of 0 when
> ID_AA64PFR1_EL1_MTE is 2 indicates that MTE_ASYNC is supported. Hence, for
> a host with ID_AA64PFR1_EL1
On Thu, 10 Apr 2025 16:10:43 +0100,
Sebastian Ott wrote:
>
> Hey,
>
> I'm seeing consistent failures for the arch_timer_edge_cases
> selftest one ampere-one(x):
> Test Assertion Failure
> arm64/arch_timer_edge_cases.c:170: timer_condition == istatus
> pid=6277 tid=6277 errno=4 - In
On Wed, 04 Sep 2024 17:17:58 +0100,
Will Deacon wrote:
>
> On Wed, Sep 04, 2024 at 01:55:03PM +0100, Joey Gouly wrote:
> > On Wed, Sep 04, 2024 at 12:43:02PM +0100, Will Deacon wrote:
> > > Right, there's quite a lot I need to do:
> > >
> > > - Uncorrupt your patches
> > > - Fix the conflict in
On Fri, 30 Aug 2024 10:05:22 +0100,
Will Deacon wrote:
>
> Hey Marc,
>
> On Fri, Aug 30, 2024 at 09:01:18AM +0100, Marc Zyngier wrote:
> > On Fri, 23 Aug 2024 14:48:11 +0100,
> > Will Deacon wrote:
> > >
> > > On Thu, Aug 22, 2024 at 04:10:51PM +0100
> >
> > Signed-off-by: Joey Gouly
> > Cc: Marc Zyngier
> > Cc: Oliver Upton
> > Cc: Catalin Marinas
> > Cc: Will Deacon
> > Reviewed-by: Marc Zyngier
> > ---
> > arch/arm64/include/asm/kvm_asm.h | 3 ++-
> > arch/arm64/kv
uction.
> >
> > Signed-off-by: Joey Gouly
> > Cc: Marc Zyngier
> > Cc: Oliver Upton
> > Cc: Catalin Marinas
> > Cc: Will Deacon
> > Reviewed-by: Marc Zyngier
> > ---
> > arch/arm64/include/asm/kvm_asm.h | 3 ++-
> > arc
On Sun, 25 Aug 2024 18:09:48 +0100,
"Russell King (Oracle)" wrote:
>
> On Sun, Aug 25, 2024 at 05:46:36PM +0100, Marc Zyngier wrote:
> > On Tue, 23 Jul 2024 08:19:59 +0100,
> > Shaoqin Huang wrote:
> > >
> > > Hi guys,
> > >
On Tue, 23 Jul 2024 03:19:59 -0400, Shaoqin Huang wrote:
> This is another try to allow userspace to change ID_AA64PFR1_EL1, and we want
> to
> give userspace the ability to control the visible feature set for a VM, which
> could be used by userspace in such a way to transparently migrate VMs.
>
On Tue, 23 Jul 2024 08:19:59 +0100,
Shaoqin Huang wrote:
>
> Hi guys,
>
> This is another try to allow userspace to change ID_AA64PFR1_EL1, and we want
> to
> give userspace the ability to control the visible feature set for a VM, which
> could be used by userspace in such a way to transparentl
> >
> > Signed-off-by: Joey Gouly
> > Cc: Marc Zyngier
> > Cc: Oliver Upton
> > Cc: Catalin Marinas
> > Cc: Will Deacon
> > Reviewed-by: Marc Zyngier
> > ---
> > arch/arm64/include/asm/kvm_asm.h | 3 ++-
> > arch/arm64/kv
On Mon, 19 Aug 2024 23:15:44 +0100,
Oliver Upton wrote:
>
> On Mon, Aug 19, 2024 at 09:33:17AM -0700, Sean Christopherson wrote:
> > And other KVM maintainers, the big question is: if we do the above, would
> > now be
> > a decent time to bite the bullet and switch to the kernel's canonical arch
On Fri, 16 Aug 2024 15:40:33 +0100,
Mark Brown wrote:
>
> [1 ]
> On Fri, Aug 16, 2024 at 03:15:19PM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > + { SYS_DESC(SYS_GCSCR_EL1), NULL, reset_val, GCSCR_EL1, 0 },
> > > + { SYS_DESC(SYS_GCSPR_
On Thu, 01 Aug 2024 13:06:41 +0100,
Mark Brown wrote:
>
> GCS introduces a number of system registers for EL1 and EL0, on systems
> with GCS we need to context switch them and expose them to VMMs to allow
> guests to use GCS.
>
> In order to allow guests to use GCS we also need to configure
> HC
On Thu, 01 Aug 2024 13:06:27 +0100,
Mark Brown wrote:
[...]
> - Don't change writability of ID_AA64PFR1_EL1 for KVM.
How does it work then?
M.
--
Without deviation from the norm, progress is not possible.
On Fri, 02 Aug 2024 22:57:53 +0100,
Mark Brown wrote:
>
> Since we already import the generated sysreg definitions from the main
> kernel and reference them in processor.h for use in other KVM tests we
> can also make use of them for get-reg-list as well instead of having hard
> coded magic numbe
nd likely wrong.
Also, this hides the horrible truth about existing ABI bugs, see
below.
> We still have a number of numerically specified registers, some of these
> are reserved registers without defined names (eg, unallocated ID registers)
> and others don't have kernel macro definit
On Fri, 02 Aug 2024 13:43:03 +0100,
Mark Brown wrote:
>
> [1 ]
> On Fri, Aug 02, 2024 at 10:00:28AM +0100, Marc Zyngier wrote:
>
> > Also, the test predates the generated stuff by some margin.
>
> Yeah, there were still defines in the main kernel source that were bei
On Thu, 01 Aug 2024 20:14:38 +0100,
Mark Brown wrote:
>
> [1 ]
> On Thu, Aug 01, 2024 at 05:45:49PM +0100, Marc Zyngier wrote:
>
> > Can we please switch all this stuff to symbolic naming instead of
> > magic numbers? Given how much effort is going into the "automa
On Wed, 31 Jul 2024 17:21:13 +0100,
Mark Brown wrote:
>
> The ID register for S1PIE is ID_AA64MMFR3_EL1.S1PIE which is bits 11:8 but
> get-reg-list uses a shift of 4, checking SCTLRX instead. Use a shift of 8
> instead.
>
> Fixes: 5f0419a0083b ("KVM: selftests: get-reg-list: add Permission
> In
On Wed, 10 Jul 2024 18:16:46 +0100,
Mark Brown wrote:
>
> [1 ]
> On Wed, Jul 10, 2024 at 04:17:02PM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > + if (ctxt_has_gcs(ctxt)) {
>
> > Since this is conditioned on S1PIE, it should be only be eval
On Tue, 25 Jun 2024 15:57:41 +0100,
Mark Brown wrote:
>
> GCS introduces a number of system registers for EL1 and EL0, on systems
> with GCS we need to context switch them and expose them to VMMs to allow
> guests to use GCS, as well as describe their fine grained traps to
> nested virtualisation
On Thu, 13 Jun 2024 09:31:45 +0100,
Shaoqin Huang wrote:
>
> If we don't care about the FEAT_CNTSC right now. Could I fix the
> compile issue and respin this again without the background of enabling
> migration between MtCollins and AmpereOne, and just keep the
> information of the different BT f
On Wed, 12 Jun 2024 06:30:51 +0100,
Oliver Upton wrote:
>
> Hi Shaoqin,
>
> On Tue, Jun 11, 2024 at 10:35:50PM -0400, Shaoqin Huang wrote:
> > Hi guys,
> >
> > I'm trying to enable migration from MtCollins(Ampere Altra, ARMv8.2+) to
> > AmpereOne(AmpereOne, ARMv8.6+), the migration always fails
On Mon, 13 May 2024 09:20:38 +0100,
Pavel Machek wrote:
>
> Hi!
>
> > Assert that accesses to a non-existent vgic-v2 CPU interface
> > consistently fail across the various KVM device attr ioctls. This also
> > serves as a regression test for a bug wherein KVM hits a NULL
> > dereference when the
On Tue, 02 Apr 2024 18:21:55 +0100,
Mark Brown wrote:
>
> On Sun, Mar 31, 2024 at 11:59:06AM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > The 2023 architecture extensions have allocated some new ID registers, add
> > > them to the KVM system regis
On Tue, 02 Apr 2024 17:20:36 +0100,
Mark Brown wrote:
>
> On Tue, Apr 02, 2024 at 03:53:33PM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > Sure, those patches are still in flight though. It does seem reasonable
> > > to target the current code.
&
On Tue, 02 Apr 2024 15:34:27 +0100,
Mark Brown wrote:
>
> [1 ]
> On Sun, Mar 31, 2024 at 11:00:41AM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > As part of the lazy FPSIMD state transitioning done by the hypervisor we
> > > currently share
On Fri, 29 Mar 2024 00:13:43 +,
Mark Brown wrote:
>
> The 2023 architecture extensions have allocated some new ID registers, add
> them to the KVM system register descriptions so that they are visible to
> guests.
>
> We make the newly introduced dpISA features writeable, as well as
> allowi
On Fri, 29 Mar 2024 00:13:42 +,
Mark Brown wrote:
>
> As part of the lazy FPSIMD state transitioning done by the hypervisor we
> currently share the userpsace FPSIMD state in thread->uw.fpsimd_state with
> the host. Since this struct is non-extensible userspace ABI we have to keep
Using the
ap(ARM64_HAS_MOPS) ? (HCRX_EL2_MSCEn |
> HCRX_EL2_MCE2) : 0))
> -#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)
> +#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM)
>
> /* TCR_EL2 Registers bits */
> #define TCR_EL2_DS (1UL << 32)
&g
On Mon, 22 Jan 2024 16:28:14 +,
Mark Brown wrote:
>
> The 2023 architecture extensions have allocated some new ID registers, add
> them to the KVM system register descriptions so that they are visible to
> guests.
>
> Signed-off-by: Mark Brown
> ---
> arch/arm64/kvm/sys_regs.c | 6 +++---
>
On Mon, 22 Jan 2024 16:28:15 +,
Mark Brown wrote:
>
> FEAT_FPMR introduces a new system register FPMR which allows configuration
> of floating point behaviour, currently for FP8 specific features. Allow use
> of this in guests, disabling the trap while guests are running and saving
> and rest
On Mon, 22 Jan 2024 16:28:06 +,
Mark Brown wrote:
>
> FEAT_FPMR defines a new EL0 accessible register FPMR use to configure the
> FP8 related features added to the architecture at the same time. Detect
> support for this register and context switch it for EL0 when present.
>
> Due to the sha
On Mon, 05 Feb 2024 13:10:26 +,
Haibo Xu wrote:
>
> Hi Marc,
>
> Could you help review the first 3 patches in this series?
For these 3 patches:
Reviewed-by: Marc Zyngier
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
On Mon, 05 Feb 2024 12:35:53 +,
Mark Brown wrote:
>
> On Mon, Feb 05, 2024 at 09:46:16AM +, Marc Zyngier wrote:
> > On Sat, 03 Feb 2024 12:25:39 +,
> > Mark Brown wrote:
>
> > > +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
> > &g
On Sat, 03 Feb 2024 12:25:39 +,
Mark Brown wrote:
>
> GCS introduces a number of system registers for EL1 and EL0, on systems
and EL2.
> with GCS we need to context switch them and expose them to VMMs to allow
> guests to use GCS, as well as describe their fine grained traps to
> nested vir
On Thu, 21 Dec 2023 02:58:40 +,
Haibo Xu wrote:
>
> On Wed, Dec 20, 2023 at 9:58 PM Marc Zyngier wrote:
> >
> > On Wed, 20 Dec 2023 13:51:24 +,
> > Haibo Xu wrote:
> > >
> > > On Wed, Dec 20, 2023 at 5:00 PM Marc Zyngier wrote:
> >
On Wed, 20 Dec 2023 13:51:24 +,
Haibo Xu wrote:
>
> On Wed, Dec 20, 2023 at 5:00 PM Marc Zyngier wrote:
> >
> > On 2023-12-20 06:50, Haibo Xu wrote:
> > > On Wed, Dec 20, 2023 at 2:22 AM Marc Zyngier wrote:
> > >>
> > >> On Tue,
On 2023-12-20 06:50, Haibo Xu wrote:
On Wed, Dec 20, 2023 at 2:22 AM Marc Zyngier wrote:
On Tue, 12 Dec 2023 09:31:20 +,
Haibo Xu wrote:
> > @@ -216,6 +221,9 @@ static bool parse_args(int argc, char *argv[])
> case 'm':
> test_
On Tue, 12 Dec 2023 09:31:20 +,
Haibo Xu wrote:
> > @@ -216,6 +221,9 @@ static bool parse_args(int argc, char *argv[])
> case 'm':
> test_args.migration_freq_ms =
> atoi_non_negative("Frequency", optarg);
> break;
> + case
On Thu, 07 Dec 2023 12:30:45 +,
Mark Brown wrote:
>
> On Thu, Dec 07, 2023 at 08:39:46AM +, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > #define HCRX_GUEST_FLAGS \
> > > - (HCRX_EL2_SMPME | HCRX_EL2_TCR2En | \
> > > + (HCRX_EL
On Tue, 05 Dec 2023 16:48:13 +,
Mark Brown wrote:
>
> FEAT_FPMR introduces a new system register FPMR which allows configuration
> of floating point behaviour, currently for FP8 specific features. Allow use
> of this in guests, disabling the trap while guests are running and saving
> and rest
Hi Joey,
On Fri, 24 Nov 2023 16:34:45 +,
Joey Gouly wrote:
>
> Hello everyone,
>
> This series implements the Permission Overlay Extension introduced in 2022
> VMSA enhancements [1]. It is based on v6.7-rc2.
>
> Changes since v2[2]:
> # Added ptrace support and selftest
> # Add
On Fri, 24 Nov 2023 16:34:51 +,
Joey Gouly wrote:
>
> Define the new system registers that POE introduces and context switch them.
Thinking about it some more, I don't think this is enough.
One fundamental thing that POE changes is that read permissions can
now be removed from S1 by the gue
On Wed, 29 Nov 2023 15:11:23 +,
Joey Gouly wrote:
>
> Hi Marc,
>
> Thanks for taking a look.
>
> On Mon, Nov 27, 2023 at 06:01:18PM +, Marc Zyngier wrote:
> > On Fri, 24 Nov 2023 16:34:51 +,
> > Joey Gouly wrote:
> > >
> > > Define
On Fri, 24 Nov 2023 16:34:51 +,
Joey Gouly wrote:
>
> Define the new system registers that POE introduces and context switch them.
I would really like to see a discussion on the respective lifetimes of
these two registers (see below).
>
> Signed-off-by: Joey Gouly
> Cc: Mar
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