This commit adds a kernel command line option using which user cfi can be
disabled.
Signed-off-by: Deepak Gupta
---
arch/riscv/kernel/usercfi.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/riscv/kernel/usercfi.c b/arch/riscv/kernel/usercfi.c
index 6e561256bfaf
On Fri, May 24, 2024 at 05:46:16PM +0800, Andy Chiu wrote:
Hi Deepak,
On Thu, Apr 4, 2024 at 7:42 AM Deepak Gupta wrote:
Shadow stack needs to be saved and restored on signal delivery and signal
return.
sigcontext embedded in ucontext is extendible. Adding cfi state in there
which can be
On Thu, May 23, 2024 at 04:59:30PM +0200, Alexandre Ghiti wrote:
Hi Deepak,
On Mon, May 13, 2024 at 7:32 PM Deepak Gupta wrote:
On Sun, May 12, 2024 at 06:31:24PM +0200, Alexandre Ghiti wrote:
>On 04/04/2024 01:35, Deepak Gupta wrote:
>>`fork` implements copy on write (COW) by mak
On Mon, May 13, 2024 at 11:36:49AM -0700, Charlie Jenkins wrote:
On Mon, May 13, 2024 at 10:47:25AM -0700, Deepak Gupta wrote:
On Fri, May 10, 2024 at 02:02:54PM -0700, Charlie Jenkins wrote:
> On Wed, Apr 03, 2024 at 04:34:58PM -0700, Deepak Gupta wrote:
> > `arch_calc_vm_prot
On Fri, May 10, 2024 at 03:33:36PM -0700, Charlie Jenkins wrote:
On Wed, Apr 03, 2024 at 04:34:50PM -0700, Deepak Gupta wrote:
Defines a base default value for envcfg per task. By default all tasks
should have cache zeroing capability. Any future base capabilities that
apply to all tasks can be
On Fri, May 10, 2024 at 04:29:19PM -0700, Charlie Jenkins wrote:
On Wed, Apr 03, 2024 at 04:35:05PM -0700, Deepak Gupta wrote:
Three architectures (x86, aarch64, riscv) have support for indirect branch
tracking feature in a very similar fashion. On a very high level, indirect
branch tracking is
On Sun, May 12, 2024 at 06:24:45PM +0200, Alexandre Ghiti wrote:
Hi Deepak,
On 04/04/2024 01:34, Deepak Gupta wrote:
`arch_calc_vm_prot_bits` is implemented on risc-v to return VM_READ |
VM_WRITE if PROT_WRITE is specified. Similarly `riscv_sys_mmap` is
updated to convert all incoming
On Fri, May 10, 2024 at 02:02:54PM -0700, Charlie Jenkins wrote:
On Wed, Apr 03, 2024 at 04:34:58PM -0700, Deepak Gupta wrote:
`arch_calc_vm_prot_bits` is implemented on risc-v to return VM_READ |
VM_WRITE if PROT_WRITE is specified. Similarly `riscv_sys_mmap` is
updated to convert all incoming
On Sun, May 12, 2024 at 06:28:59PM +0200, Alexandre Ghiti wrote:
On 04/04/2024 01:35, Deepak Gupta wrote:
pte_mkwrite creates PTEs with WRITE encodings for underlying arch.
Underlying arch can have two types of writeable mappings. One that can be
written using regular store instructions
On Sun, May 12, 2024 at 06:31:24PM +0200, Alexandre Ghiti wrote:
On 04/04/2024 01:35, Deepak Gupta wrote:
`fork` implements copy on write (COW) by making pages readonly in child
and parent both.
ptep_set_wrprotect and pte_wrprotect clears _PAGE_WRITE in PTE.
Assumption is that page is readable
On Sun, May 12, 2024 at 06:50:18PM +0200, Alexandre Ghiti wrote:
On 04/04/2024 01:35, Deepak Gupta wrote:
As discussed extensively in the changelog for the addition of this
syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall") the
existing mmap() and madvise() syscalls
On Sun, May 12, 2024 at 07:05:27PM +0200, Alexandre Ghiti wrote:
On 04/04/2024 01:35, Deepak Gupta wrote:
Userspace specifies VM_CLONE to share address space and spawn new thread.
CLONE_VM?
Yes I meant CLONE_VM, will fix it.
`clone` allow userspace to specify a new stack for new
On Fri, May 10, 2024 at 01:30:32PM -0700, Charlie Jenkins wrote:
On Wed, Apr 03, 2024 at 04:35:15PM -0700, Deepak Gupta wrote:
Adding documentation on landing pad aka indirect branch tracking on riscv
and kernel interfaces exposed so that user tasks can enable it.
Signed-off-by: Deepak Gupta
On Thu, May 09, 2024 at 09:32:49PM +0100, Conor Dooley wrote:
On Thu, May 09, 2024 at 11:46:26AM -0700, Deepak Gupta wrote:
On Thu, May 09, 2024 at 07:14:26PM +0100, Conor Dooley wrote:
> On Tue, Apr 16, 2024 at 08:44:16AM -0700, Deepak Gupta wrote:
> > On Mon, Apr 15, 2024 at 02:41:0
On Thu, May 09, 2024 at 11:21:15AM -0700, Charlie Jenkins wrote:
On Wed, Apr 03, 2024 at 04:35:17PM -0700, Deepak Gupta wrote:
+
+int main(int argc, char *argv[])
+{
+ int ret = 0;
+ unsigned long lpad_status = 0, ss_status = 0;
+
+ ksft_print_header();
+
+ ksft_set_plan
On Wed, May 08, 2024 at 05:10:46PM -0700, Charlie Jenkins wrote:
On Wed, Apr 03, 2024 at 04:34:49PM -0700, Deepak Gupta wrote:
envcfg CSR defines enabling bits for cache management instructions and
soon will control enabling for control flow integrity and pointer
masking features.
Control flow
On Thu, May 09, 2024 at 07:14:26PM +0100, Conor Dooley wrote:
On Tue, Apr 16, 2024 at 08:44:16AM -0700, Deepak Gupta wrote:
On Mon, Apr 15, 2024 at 02:41:05PM -0500, Rob Herring wrote:
> On Wed, Apr 10, 2024 at 02:37:21PM -0700, Deepak Gupta wrote:
> > On Wed, Apr 10, 2024 at 4:
On Wed, Apr 10, 2024 at 11:27:16PM +0100, Conor Dooley wrote:
On Wed, Apr 10, 2024 at 11:16:11PM +0100, Conor Dooley wrote:
On Wed, Apr 10, 2024 at 02:32:41PM -0700, Deepak Gupta wrote:
> On Wed, Apr 10, 2024 at 11:11:00AM +0200, Clément Léger wrote:
> > Add parsing for Zcmop ISA
On Mon, Apr 08, 2024 at 10:01:12AM +0200, Clément Léger wrote:
On 05/04/2024 19:33, Deepak Gupta wrote:
On Fri, Apr 5, 2024 at 8:26 AM Andrew Jones wrote:
On Thu, Apr 04, 2024 at 12:32:46PM +0200, Clément Léger wrote:
The Zimop ISA extension was ratified recently. This series adds support
On Wed, Apr 10, 2024 at 4:58 AM Rob Herring wrote:
>
> On Wed, Apr 03, 2024 at 04:34:52PM -0700, Deepak Gupta wrote:
> > Make an entry for cfi extensions in extensions.yaml.
> >
> > Signed-off-by: Deepak Gupta
> > ---
> > .../devicetree/bindings
For the series:
Reviewed-by: Deepak Gupta
On Wed, Apr 10, 2024 at 2:13 AM Clément Léger wrote:
>
> Add support for (yet again) more RVA23U64 missing extensions. Add
> support for Zcmop, Zca, Zcf, Zcd and Zcb extensions isa string parsing,
> hwprobe and kvm support. Zce, Z
On Wed, Apr 10, 2024 at 11:11:00AM +0200, Clément Léger wrote:
Add parsing for Zcmop ISA extension which was ratified in commit
b854a709c00 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
Signed-off-by: Clément Léger
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1
On Fri, Apr 5, 2024 at 8:26 AM Andrew Jones wrote:
>
> On Thu, Apr 04, 2024 at 12:32:46PM +0200, Clément Léger wrote:
> > The Zimop ISA extension was ratified recently. This series adds support
> > for parsing it from riscv,isa, hwprobe export and kvm support for
> > Guest/VM.
>
> I'm not sure we
On Thu, Apr 04, 2024 at 09:02:17PM +0200, David Hildenbrand wrote:
On 04.04.24 01:34, Deepak Gupta wrote:
}
- } else if (!(vm_flags & VM_READ)) {
+ } else if (!(vm_flags & VM_READ) && !vma_is_shadow_stack(vm_flags)) {
+ /* reads allowed if its
On Thu, Apr 4, 2024 at 12:15 PM David Hildenbrand wrote:
>
> On 04.04.24 21:04, Mark Brown wrote:
> > On Thu, Apr 04, 2024 at 08:58:06PM +0200, David Hildenbrand wrote:
> >
> >> or even introduce some ARCH_HAS_SHADOW_STACK so we can remove these
> >> arch-specific thingies here.
> >
> > It would b
test. Make sure signal delivery results in token creation on
shadow stack and consumes (and verifies) token on sigreturn
- shadow stack protection test. attempts to write using regular store
instruction on shadow stack memory must result in access faults
Signed-off-by: Deepak
Adding documentation on shadow stack for user mode on riscv and kernel
interfaces exposed so that user tasks can enable it.
Signed-off-by: Deepak Gupta
---
Documentation/arch/riscv/zicfiss.rst | 169 +++
1 file changed, 169 insertions(+)
create mode 100644 Documentation
Adding documentation on landing pad aka indirect branch tracking on riscv
and kernel interfaces exposed so that user tasks can enable it.
Signed-off-by: Deepak Gupta
---
Documentation/arch/riscv/zicfilp.rst | 104 +++
1 file changed, 104 insertions(+)
create mode 100644
support cpu assisted user mode cfi.
Signed-off-by: Deepak Gupta
---
arch/riscv/Kconfig | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7e0b2bcc388f..d6f1303ef660 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -203,6
Adding enumeration of zicfilp and zicfiss extensions in hwprobe syscall.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_hwprobe.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h
b/arch/riscv
allowed via ptrace set interface. However setting `elp` state or
setting shadow stack pointer are allowed via ptrace set interface. It is
expected `gdb` might have use to fixup `elp` state or `shadow stack`
pointer.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/uapi/asm/ptrace.h | 18
on sigreturn, kernel retrieves token from top of
shadow stack and validates it. This allows that user mode can't arbitrary
pivot to any shadow stack address without having a token and thus provide
strong security assurance between signaly delivery and sigreturn window.
Signed-off-by: Deepak
Shadow stack needs to be saved and restored on signal delivery and signal
return.
sigcontext embedded in ucontext is extendible. Adding cfi state in there
which can be used to save cfi state before signal delivery and restore
cfi state on sigreturn
Signed-off-by: Deepak Gupta
---
arch/riscv
(on execution of `sspopchk`).
In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR.
SEGV_CPERR was introduced by x86 shadow stack patches.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/asm-prototypes.h | 1 +
arch/riscv/kernel/entry.S | 3 ++
arch/riscv/kernel
Updating __show_regs to print captured shadow stack pointer as well.
On tasks where shadow stack is disabled, it'll simply print 0.
Signed-off-by: Deepak Gupta
---
arch/riscv/kernel/process.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/proces
prctls implemented are:
PR_SET_INDIR_BR_LP_STATUS, PR_GET_INDIR_BR_LP_STATUS and
PR_LOCK_INDIR_BR_LP_STATUS.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/usercfi.h | 22 -
arch/riscv/kernel/process.c | 5 +++
arch/riscv/kernel/usercfi.c | 76
PR_SHADOW_STACK_ENABLE is implemented because RISCV allows each mode to
write to their own shadow stack using `sspush` or `ssamoswap`.
PR_LOCK_SHADOW_STACK_STATUS locks current configuration of shadow stack
enabling.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/usercfi.h | 18 +-
arch/riscv/kernel
.
- PR_LOCK_INDIR_BR_LP_STATUS: Locks configured status for indirect branch
tracking for user thread.
Signed-off-by: Deepak Gupta
---
include/uapi/linux/prctl.h | 27 +++
kernel/sys.c | 30 ++
2 files changed, 57 insertions(+)
diff --git a
Deepak Gupta but later
modified by Mark Brown for arm's GCS patch series.
Signed-off-by: Mark Brown
Co-developed-by: Deepak Gupta
---
include/linux/mm.h | 3 +++
include/uapi/linux/prctl.h | 22 ++
kernel/sys.c | 30
provided. This is not settled yet and being
extensively discussed on mailing list. Once that's settled, this commit
will adapt to that.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/usercfi.h | 39 ++
arch/riscv/kernel/process.c | 12 ++-
arch/riscv/kernel/user
setup by kernel because user mode can do that by itself. However to
provide compatibility and portability with other architectues, user mode
can specify token set flag.
Signed-off-by: Deepak Gupta
---
arch/riscv/kernel/Makefile | 2 +
arch/riscv/kernel/user
d-off-by: Deepak Gupta
---
arch/riscv/include/asm/pgtable.h | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 9b837239d3e8..7a1c2a98d272 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b
can select write PTE encoding based on VMA range (i.e.
VM_SHADOW_STACK)
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/pgtable.h | 7 +++
arch/riscv/mm/pgtable.c | 21 +
2 files changed, 28 insertions(+)
diff --git a/arch/riscv/include/asm/pgtable.h b
This patch implements creating shadow stack pte (on riscv). Creating
shadow stack PTE on riscv means that clearing RWX and then setting W=1.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/pgtable.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/include/asm
encodings.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/mman.h| 24
arch/riscv/include/asm/pgtable.h | 1 +
arch/riscv/kernel/sys_riscv.c| 11 +++
arch/riscv/mm/init.c | 2 +-
mm/mmap.c| 1 +
5 files changed, 38
-off-by: Deepak Gupta
Suggested-by: Mike Rapoport
---
include/linux/mm.h | 13 -
mm/gup.c | 5 +++--
mm/internal.h | 2 +-
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 64109f6c70f5..9952937be659 100644
:
https://lore.kernel.org/lkml/20231009-arm64-gcs-v6-12-78e55deaa...@kernel.org/#r
Signed-off-by: Deepak Gupta
---
fs/proc/task_mmu.c | 3 +++
include/linux/mm.h | 11 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
index
shadow stack, that means that it needs to be
supported. And thus save/restore of shadow stack pointer in entry.S instead
of in `switch_to.h`.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/processor.h | 1 +
arch/riscv/include/asm/thread_info.h | 3 +++
arch/riscv/include/asm/use
-by: Deepak Gupta
---
arch/riscv/include/asm/csr.h | 16
1 file changed, 16 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index bbd2207adb39..3bb126d1c5ff 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -18,6
feature bitmap. Furthermore this patch adds detection
utility functions to return whether shadow stack or landing pads are
supported by cpu.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/cpufeature.h | 13 +
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/include/asm
Make an entry for cfi extensions in extensions.yaml.
Signed-off-by: Deepak Gupta
---
.../devicetree/bindings/riscv/extensions.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml
b/Documentation/devicetree
riscv will need an implementation for exit_thread to clean up shadow stack
when thread exits. If current thread had shadow stack enabled, shadow
stack is allocated by default for any new thread.
Signed-off-by: Deepak Gupta
---
arch/riscv/Kconfig | 1 +
arch/riscv/kernel/process.c | 5
Defines a base default value for envcfg per task. By default all tasks
should have cache zeroing capability. Any future base capabilities that
apply to all tasks can be turned on same way.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/csr.h | 2 ++
arch/riscv/kernel/process.c | 6
.
This patch creates a place holder for envcfg CSR in `thread_info` and
adds logic to save and restore on task switching.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/switch_to.h | 10 ++
arch/riscv/include/asm/thread_info.h | 1 +
2 files changed, 11 insertions(+)
diff --git a
Sending out v3 for cpu assisted riscv user mode control flow integrity.
v2 [9] was sent a week ago for this riscv usermode control flow integrity
enabling. RFC patchset was (v1) early this year (January) [7].
changes in v3
--
envcfg:
logic to pick up base envcfg had a bug where `ENVCF
On Mon, Apr 1, 2024 at 10:34 AM Deepak Gupta wrote:
>
> On Mon, Apr 1, 2024 at 2:48 AM Muhammad Usama Anjum
> wrote:
> >
> > >>> Signed-off-by: Deepak Gupta
> > >>> ---
> > >>> tools/testing/selftests/riscv/Makefile| 2 +-
On Mon, Apr 1, 2024 at 2:48 AM Muhammad Usama Anjum
wrote:
>
> >>> Signed-off-by: Deepak Gupta
> >>> ---
> >>> tools/testing/selftests/riscv/Makefile| 2 +-
> >>> tools/testing/selftests/riscv/cfi/Makefile| 10 +
> &g
On Fri, Mar 29, 2024 at 12:50 PM Muhammad Usama Anjum
wrote:
>
> On 3/29/24 9:44 AM, Deepak Gupta wrote:
> > Adds kselftest for RISC-V control flow integrity implementation for user
> > mode. There is not a lot going on in kernel for enabling landing pad for
> > user mod
On Thu, Mar 28, 2024 at 9:46 PM Deepak Gupta wrote:
>
> pte_mkwrite creates PTEs with WRITE encodings for underlying arch. Underlying
> arch can have two types of writeable mappings. One that can be written using
> regular store instructions. Another one that can only be w
> >
> > +- const: zicfilp
> > + description:
> > +The standard Zicfilp extension for enforcing forward edge
> > control-flow
> > +integrity as ratified in commit 0036ff2 of riscv-cfi.
> > +
> > +- const: zicfiss
> > + description:
> > +
) token on sigreturn
- shadow stack protection test. attempts to write using regular store
instruction on shadow stack memory must result in access faults
Signed-off-by: Deepak Gupta
---
tools/testing/selftests/riscv/Makefile| 2 +-
tools/testing/selftests/riscv/cfi/Makefile
Adding documentation on shadow stack for user mode on riscv and kernel
interfaces exposed so that user tasks can enable it.
Signed-off-by: Deepak Gupta
---
Documentation/arch/riscv/zicfiss.rst | 169 +++
1 file changed, 169 insertions(+)
create mode 100644 Documentation
Adding documentation on landing pad aka indirect branch tracking on riscv
and kernel interfaces exposed so that user tasks can enable it.
Signed-off-by: Deepak Gupta
---
Documentation/arch/riscv/zicfilp.rst | 104 +++
1 file changed, 104 insertions(+)
create mode 100644
support
cpu assisted user mode cfi.
Signed-off-by: Deepak Gupta
---
arch/riscv/Kconfig | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7e0b2bcc388f..d6f1303ef660 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -203,6
allowed via ptrace set interface. However setting `elp` state or
setting shadow stack pointer are allowed via ptrace set interface. It is
expected `gdb` might have use to fixup `elp` state or `shadow stack`
pointer.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/uapi/asm/ptrace.h | 18
on sigreturn, kernel retrieves token from top of shadow stack and
validates it. This allows that user mode can't arbitrary pivot to any shadow
stack address without having a token and thus provide strong security assurance
between signaly delivery and sigreturn window.
Signed-off-by: Deepak
Shadow stack needs to be saved and restored on signal delivery and signal
return.
sigcontext embedded in ucontext is extendible. Adding cfi state in there
which can be used to save cfi state before signal delivery and restore
cfi state on sigreturn
Signed-off-by: Deepak Gupta
---
arch/riscv
(on execution of `sspopchk`)
In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR. SEGV_CPERR was
introduced by x86 shadow stack patches.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/asm-prototypes.h | 1 +
arch/riscv/kernel/entry.S | 3 ++
arch/riscv/kernel
Updating __show_regs to print captured shadow stack pointer as well.
On tasks where shadow stack is disabled, it'll simply print 0.
Signed-off-by: Deepak Gupta
---
arch/riscv/kernel/process.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/proces
prctls implemented are PR_SET_INDIR_BR_LP_STATUS / PR_GET_INDIR_BR_LP_STATUS
and PR_LOCK_INDIR_BR_LP_STATUS.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/usercfi.h | 22 -
arch/riscv/kernel/process.c | 5 +++
arch/riscv/kernel/usercfi.c | 76
PR_SHADOW_STACK_ENABLE is implemented because RISCV allows each mode to write
to their own shadow stack using `sspush` or `ssamoswap`.
PR_LOCK_SHADOW_STACK_STATUS locks current configuration of shadow stack
enabling.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/usercfi.h | 18 +-
arch/riscv/kernel
.
- PR_LOCK_INDIR_BR_LP_STATUS: Locks configured status for indirect branch
tracking for user thread.
Signed-off-by: Deepak Gupta
---
include/uapi/linux/prctl.h | 27 +++
kernel/sys.c | 30 ++
2 files changed, 57 insertions
Deepak Gupta but later
modified by Mark Brown for arm's GCS patch series.
Signed-off-by: Mark Brown
Co-developed-by: Deepak Gupta
Signed-off-by: Deepak Gupta
---
include/linux/mm.h | 3 +++
include/uapi/linux/prctl.h | 22 ++
kernel/sys.c
provided. This is not settled yet and being
extensively discussed on mailing list. Once that's settled, this commit
will adapt to that.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/usercfi.h | 39 ++
arch/riscv/kernel/process.c | 12 +++
arch/riscv/kernel/user
setup by kernel because user mode can do that by itself. However to
provide compatiblity and portability with other architectues, user mode can
specify token set flag.
Signed-off-by: Deepak Gupta
---
arch/riscv/kernel/Makefile | 2 +
arch/riscv/kernel/user
d-off-by: Deepak Gupta
---
arch/riscv/include/asm/pgtable.h | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 9b837239d3e8..7a1c2a98d272 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b
can select write PTE
encoding based on VMA range.
On riscv, presence of only VM_WRITE in vma->vm_flags means it's a shadow stack.
Signed-off-by: Deepak Gupta
rebase with a30f0ca0fa31cdb2ac3d24b7b5be9e3ae75f4175
Implementation of pte_mkwrite and pmd_mkwrite on riscv
Signed-off-by: Deep
This patch implements creating shadow stack pte (on riscv). Creating
shadow stack PTE on riscv means that clearing RWX and then setting W=1.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/pgtable.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/include/asm
encodings.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/mman.h| 24
arch/riscv/include/asm/pgtable.h | 1 +
arch/riscv/kernel/sys_riscv.c| 11 +++
arch/riscv/mm/init.c | 2 +-
mm/mmap.c| 1 +
5 files changed, 38
each arch specific.
Signed-off-by: Deepak Gupta
---
include/linux/mm.h | 12 +++-
mm/gup.c | 5 +++--
mm/internal.h | 2 +-
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 225af437ecba..9e6a4fbfccac 100644
same.
Signed-off-by: Deepak Gupta
---
include/linux/mm.h | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index f5a97dec5169..225af437ecba 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -352,7 +352,25
kernel shadow stack, that means that it needs to be supported.
And thus save/restore of shadow stack pointer in entry.S instead of in
`switch_to.h`.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/processor.h | 1 +
arch/riscv/include/asm/thread_info.h | 3 +++
arch/riscv/include/asm/use
-by: Deepak Gupta
---
arch/riscv/include/asm/csr.h | 16
1 file changed, 16 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index bbd2207adb39..3bb126d1c5ff 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -18,6
device tree and accordinlgy lights
up bit in cpu feature bitmap. Furthermore this patch adds detection utility
functions to return whether shadow stack or landing pads are supported by
cpu.
Signed-off-by: Deepak Gupta
---
.../devicetree/bindings/riscv/extensions.yaml | 10 ++
arch/riscv
riscv will need an implementation for exit_thread to clean up shadow stack
when thread exits. If current thread had shadow stack enabled, shadow
stack is allocated by default for any new thread.
Signed-off-by: Deepak Gupta
---
arch/riscv/Kconfig | 1 +
arch/riscv/kernel/process.c | 5
Defines a base default value for envcfg per task. By default all tasks
should have cache zeroing capability. Any future base capabilities that
apply to all tasks can be turned on same way.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/csr.h | 2 ++
arch/riscv/kernel/process.c | 1 +
2
.
This patch creates a place holder for envcfg CSR in `thread_info` and adds
logic to save and restore on task switching.
Signed-off-by: Deepak Gupta
---
arch/riscv/include/asm/switch_to.h | 10 ++
arch/riscv/include/asm/thread_info.h | 1 +
2 files changed, 11 insertions(+)
diff --git a
mm/20231122-arm64-gcs-v7-2-201c483bd...@kernel.org/
[7] - https://lore.kernel.org/lkml/20240125062739.1339782-1-de...@rivosinc.com/
[8] -
https://docs.google.com/spreadsheets/d/1_cHGH4ctNVvFRiS7hW9dEGKtXLAJ3aX4Z_iTSa3Tw2U/edit#gid=0
Deepak Gupta (26):
riscv: envcfg save and restore on task swit
On Tue, Feb 13, 2024 at 11:34:59AM +0100, David Hildenbrand wrote:
On 25.01.24 18:07, Deepak Gupta wrote:
On Thu, Jan 25, 2024 at 09:18:07AM +0100, David Hildenbrand wrote:
On 25.01.24 07:21, de...@rivosinc.com wrote:
From: Deepak Gupta
x86 has used VM_SHADOW_STACK (alias to VM_HIGH_ARCH_5
On Fri, Feb 09, 2024 at 08:44:53PM +, Edgecombe, Rick P wrote:
On Wed, 2024-01-24 at 22:21 -0800, de...@rivosinc.com wrote:
From: Deepak Gupta
As discussed extensively in the changelog for the addition of this
syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall") th
On Tue, Feb 06, 2024 at 04:01:28PM +, Mark Brown wrote:
On Wed, Jan 24, 2024 at 10:21:40PM -0800, de...@rivosinc.com wrote:
As discussed extensively in the changelog for the addition of this
syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall") the
existing mmap() and madvise() s
On Tue, Feb 06, 2024 at 04:13:39PM +, Mark Brown wrote:
On Wed, Jan 24, 2024 at 10:21:43PM -0800, de...@rivosinc.com wrote:
To allow userspace to enable this feature for itself, following prtcls are
defined:
- PR_GET_INDIR_BR_LP_STATUS: Gets current configured status for indirect branch
On Fri, Feb 09, 2024 at 08:44:35PM +, Edgecombe, Rick P wrote:
On Wed, 2024-01-24 at 22:21 -0800, de...@rivosinc.com wrote:
+ /*
+ * PROT_SHADOWSTACK is a kernel only protection flag on risc-
v.
+ * mmap doesn't expect PROT_SHADOWSTACK to be set by user
space.
+ *
uggested-by: David Hildenbrand
> Acked-by: David Hildenbrand
> Signed-off-by: Mark Brown
Reviewed-by: Deepak Gupta
On Fri, Feb 2, 2024 at 4:05 PM Mark Brown wrote:
>
> There are a number of architectures with shadow stack features which we are
> presenting to userspace with as consistent an API as we can (though there
> are some architecture specifics). Especially given that there are some
> important consider
On Thu, Jan 25, 2024 at 01:24:16PM -0800, Charlie Jenkins wrote:
On Wed, Jan 24, 2024 at 10:21:40PM -0800, de...@rivosinc.com wrote:
From: Deepak Gupta
As discussed extensively in the changelog for the addition of this
syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall&
On Thu, Jan 25, 2024 at 02:47:49PM -0500, Stefan O'Rear wrote:
On Thu, Jan 25, 2024, at 12:30 PM, Deepak Gupta wrote:
On Thu, Jan 25, 2024 at 02:29:01AM -0500, Stefan O'Rear wrote:
On Thu, Jan 25, 2024, at 1:21 AM, de...@rivosinc.com wrote:
From: Deepak Gupta
Carves out spa
On Thu, Jan 25, 2024 at 06:44:48PM +, Conor Dooley wrote:
On Thu, Jan 25, 2024 at 10:12:16AM -0800, Deepak Gupta wrote:
On Thu, Jan 25, 2024 at 06:04:26PM +, Conor Dooley wrote:
> On Wed, Jan 24, 2024 at 10:21:49PM -0800, de...@rivosinc.com wrote:
> > From: Deepak Gupta
>
On Thu, Jan 25, 2024 at 05:59:24PM +, Conor Dooley wrote:
Yo,
Series is RFC, so not gonna review it in depth, just wanted to comment
on this particular patch.
On Wed, Jan 24, 2024 at 10:21:30PM -0800, de...@rivosinc.com wrote:
From: Deepak Gupta
This patch adds support for detecting
On Thu, Jan 25, 2024 at 06:04:26PM +, Conor Dooley wrote:
On Wed, Jan 24, 2024 at 10:21:49PM -0800, de...@rivosinc.com wrote:
From: Deepak Gupta
This patch selects config shadow stack support and landing pad instr
support. Shadow stack support and landing instr support is hidden behind
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