On Mon, Aug 19, 2024 at 04:06:08PM -0700, Charlie Jenkins wrote:
> On Tue, Aug 13, 2024 at 04:55:27PM +0100, Conor Dooley wrote:
> > On Mon, Aug 12, 2024 at 05:45:30PM -0700, Charlie Jenkins wrote:
> > > On Fri, Aug 09, 2024 at 11:31:15PM +0100, Conor Dooley wrote:
> > >
On Mon, Aug 12, 2024 at 05:45:30PM -0700, Charlie Jenkins wrote:
> On Fri, Aug 09, 2024 at 11:31:15PM +0100, Conor Dooley wrote:
> > On Tue, Aug 06, 2024 at 05:31:36PM -0700, Charlie Jenkins wrote:
> > > xtheadvector is a custom extension that is based upon riscv vector
>
On Tue, Aug 06, 2024 at 05:31:36PM -0700, Charlie Jenkins wrote:
> xtheadvector is a custom extension that is based upon riscv vector
> version 0.7.1 [1]. All of the vector routines have been modified to
> support this alternative vector version based upon whether xtheadvector
> was determined to b
On Tue, Jul 02, 2024 at 05:46:42PM +0800, Yu-Chien Peter Lin wrote:
> On Mon, Jul 01, 2024 at 05:31:01PM +0100, Conor Dooley wrote:
> > On Mon, Jul 01, 2024 at 11:11:55AM -0500, Samuel Holland wrote:
> > > Hi Conor, Charlie,
> > >
> > > On 2024-07-01 11:07 AM
On Mon, Jul 01, 2024 at 11:11:55AM -0500, Samuel Holland wrote:
> Hi Conor, Charlie,
>
> On 2024-07-01 11:07 AM, Conor Dooley wrote:
> > On Mon, Jul 01, 2024 at 10:27:01AM -0500, Samuel Holland wrote:
> >> On 2024-06-19 6:57 PM, Charlie Jenkins wrote:
> >>> The
t; Signed-off-by: Charlie Jenkins
> > Reviewed-by: Conor Dooley
> > ---
> > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++-
>
> The other C906/C910/C920-based SoCs need devicetree updates as well, although
> they don't necessarily need to be part of this series:
&
On Wed, Jun 19, 2024 at 04:57:18PM -0700, Charlie Jenkins wrote:
> If thead,vlenb is provided in the device tree, prefer that over reading
> the vlenb csr.
>
> Signed-off-by: Charlie Jenkins
Acked-by: Conor Dooley
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On Wed, Jun 19, 2024 at 01:35:11PM +0200, Clément Léger wrote:
> Add description for the Zimop (May-Be-Operations) ISA extension which
> was ratified in commit 58220614a5f of the riscv-isa-manual.
>
> Signed-off-by: Clément Léger
> Reviewed-by: Charlie Jenkins
Acked-b
On Mon, Jun 24, 2024 at 10:24:51AM +0200, Clément Léger wrote:
>
>
> On 23/06/2024 17:42, Conor Dooley wrote:
> > On Wed, Jun 19, 2024 at 01:35:18PM +0200, Clément Léger wrote:
> >> The Zc* standard extension for code reduction introduces new extensions.
> >> Thi
mbedded CPUs instead of application processors.
>
> Signed-off-by: Clément Léger
> Reviewed-by: Conor Dooley
> ---
> arch/riscv/include/asm/hwcap.h | 4 +++
> arch/riscv/kernel/cpufeature.c | 55 +-
> 2 files changed, 58 insertions(+), 1 d
On Wed, Jun 19, 2024 at 05:39:08PM +0200, Clément Léger wrote:
> Add description for the Zaamo and Zalrsc ISA extension[1].
>
> Link: https://github.com/riscv/riscv-zaamo-zalrsc [1]
> Signed-off-by: Clément Léger
Acked-by: Conor Dooley
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On Wed, Jun 19, 2024 at 05:39:09PM +0200, Clément Léger wrote:
> These 2 new extensions are actually a subset of the A extension which
> provides atomic memory operations and load-reserved/store-conditional
> instructions.
I wish this silly degree of fragmentation didn't exist.
A
Andy,
On Mon, Jun 10, 2024 at 03:56:46PM -0700, Charlie Jenkins wrote:
> Use alternatives to add support for xtheadvector vector save/restore
> routines.
>
> Signed-off-by: Charlie Jenkins
Could you review this please?
Cheers,
Conor.
> ---
> arch/riscv/include/asm/csr.h | 6 +
>
U applies to all possible CPUs. On T-Head CPUs implementing
> pre-ratification vector, reading the th.vlenb CSR may produce an illegal
> instruction trap, so this property is required on such systems.
>
> Signed-off-by: Charlie Jenkins
Reviewed-by: Conor Dooley
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On Mon, Jun 10, 2024 at 03:56:40PM -0700, Charlie Jenkins wrote:
> The D1/D1s SoCs support xtheadvector so it can be included in the
> devicetree. Also include vlenb for the cpu.
>
> Signed-off-by: Charlie Jenkins
Reviewed-by: Conor Dooley
> ---
> arch/riscv/boot/dt
On Mon, Jun 10, 2024 at 03:56:41PM -0700, Charlie Jenkins wrote:
> Add support to the kernel for THead vendor extensions with the target of
> the new extension xtheadvector.
>
> Signed-off-by: Charlie Jenkins
Reviewed-by: Conor Dooley
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On Mon, Jun 10, 2024 at 03:56:45PM -0700, Charlie Jenkins wrote:
> xtheadvector uses different encodings than standard vector for
> vsetvli and vector loads/stores. Write the instruction formats to be
> used in assembly code.
>
> Co-developed-by: Heiko Stuebner
> Signed-off-by: Charlie Jenkins
On Mon, Jun 10, 2024 at 09:38:06AM -0700, Charlie Jenkins wrote:
> On Mon, Jun 10, 2024 at 05:29:23PM +0100, Conor Dooley wrote:
> > On Sun, Jun 09, 2024 at 09:45:07PM -0700, Charlie Jenkins wrote:
> > > Add a property analogous to the vlenb CSR so that software can detect
>
On Sun, Jun 09, 2024 at 09:45:07PM -0700, Charlie Jenkins wrote:
> Add a property analogous to the vlenb CSR so that software can detect
> the vector length of each CPU prior to it being brought online.
> Currently software has to assume that the vector length read from the
> boot CPU applies to al
On Thu, May 30, 2024 at 02:35:51PM -0700, Palmer Dabbelt wrote:
> On Thu, 09 May 2024 09:26:56 PDT (-0700), andy.c...@sifive.com wrote:
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c
> > b/arch/riscv/kernel/sys_hwprobe.c
> > index 969ef3d59dbe..35390b4a5a17 100644
> > --- a/arch/riscv/kernel/sys
__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0
> : -EPROBE_DEFER;
> +}
Could you write the logic in these out normally please? I think they'd
be more understandable (particular this second one) broken down and with
early return.
Otherwise,
Reviewed-by: Conor Dool
are modified to use this validation mechanism.
I wish we weren't doin' it at all, but since we have to, I think what
you've got here is good.
Reviewed-by: Conor Dooley
Do you want me to send some patches for the F/V stuff we discussed
previously?
Cheers,
Conor.
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On Thu, May 16, 2024 at 01:28:45PM -0700, Charlie Jenkins wrote:
> On Thu, May 16, 2024 at 05:24:25PM +0100, Conor Dooley wrote:
> > On Thu, May 16, 2024 at 10:00:12PM +0800, Andy Chiu wrote:
> > > On Sat, May 4, 2024 at 2:21 AM Charlie Jenkins
> > > wrote:
>
On Thu, May 16, 2024 at 10:00:12PM +0800, Andy Chiu wrote:
> On Sat, May 4, 2024 at 2:21 AM Charlie Jenkins wrote:
> > + if (elf_hwcap & COMPAT_HWCAP_ISA_V &&
> > has_riscv_homogeneous_vlenb() < 0) {
> > + pr_warn("Unsupported heterogeneous vlen detected,
> >
On Wed, May 15, 2024 at 03:26:23PM +0200, Clément Léger wrote:
> > This function is badly in need of some new variable names for the first
> > two parameters. It's hard to follow what each of them is meant to be
> > once you're inside this function and removed from their definitions.
> > The first
On Mon, Apr 29, 2024 at 05:04:55PM +0200, Clément Léger wrote:
> Since a few extensions (Zicbom/Zicboz) already needs validation and
> future ones will need it as well (Zc*) add a validate() callback to
> struct riscv_isa_ext_data. This require to rework the way extensions are
> parsed and split it
On Tue, May 14, 2024 at 02:48:01PM +0200, Clément Léger wrote:
>
>
> On 14/05/2024 14:43, Conor Dooley wrote:
> > On Tue, May 14, 2024 at 09:53:08AM +0200, Clément Léger wrote:
> >>
> >>
> >> On 30/04/2024 13:44, Conor Dooley wrote:
> >>> O
On Tue, May 14, 2024 at 09:53:08AM +0200, Clément Léger wrote:
>
>
> On 30/04/2024 13:44, Conor Dooley wrote:
> > On Tue, Apr 30, 2024 at 09:18:47AM +0200, Clément Léger wrote:
> >>
> >>
> >> On 30/04/2024 00:15, Conor Dooley wrote:
> >>> O
On Fri, May 10, 2024 at 02:25:26PM -0700, Charlie Jenkins wrote:
> On Fri, May 10, 2024 at 09:50:32PM +0100, Conor Dooley wrote:
> > On Tue, May 07, 2024 at 06:03:19PM +0100, Conor Dooley wrote:
> > > On Fri, May 03, 2024 at 11:18:21AM -0700, Charlie Jenkins wrote:
> >
On Tue, May 07, 2024 at 06:03:19PM +0100, Conor Dooley wrote:
> On Fri, May 03, 2024 at 11:18:21AM -0700, Charlie Jenkins wrote:
> > All of the supported vendor extensions that have been listed in
> > riscv_isa_vendor_ext_list can be exported through /proc/cpuinfo.
> >
>
On Thu, May 09, 2024 at 09:25:25AM +0100, Conor Dooley wrote:
> On Thu, May 09, 2024 at 08:48:09AM +0100, Conor Dooley wrote:
> > On Thu, May 09, 2024 at 02:56:30PM +0800, Andy Chiu wrote:
> > > Hi Conor,
> > >
> > > Should we check if "v&
On Thu, May 09, 2024 at 11:46:26AM -0700, Deepak Gupta wrote:
> On Thu, May 09, 2024 at 07:14:26PM +0100, Conor Dooley wrote:
> > On Tue, Apr 16, 2024 at 08:44:16AM -0700, Deepak Gupta wrote:
> > > On Mon, Apr 15, 2024 at 02:41:05PM -0500, Rob Herring wrote:
> > > >
On Tue, Apr 16, 2024 at 08:44:16AM -0700, Deepak Gupta wrote:
> On Mon, Apr 15, 2024 at 02:41:05PM -0500, Rob Herring wrote:
> > On Wed, Apr 10, 2024 at 02:37:21PM -0700, Deepak Gupta wrote:
> > > On Wed, Apr 10, 2024 at 4:58 AM Rob Herring wrote:
> > > >
> > > > On Wed, Apr 03, 2024 at 04:34:52PM
On Thu, May 09, 2024 at 08:48:09AM +0100, Conor Dooley wrote:
> On Thu, May 09, 2024 at 02:56:30PM +0800, Andy Chiu wrote:
> > Hi Conor,
> >
> > Should we check if "v" presents for vector crypto extensions in
> > riscv_isa_extension_check()? We are not c
e xtheadvector vendor extension is added using these changes.
>
> Signed-off-by: Charlie Jenkins
I thought that I had reviewed this the other day,
Reviewed-by: Conor Dooley
Cheers,
Conor.
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between different series here at
the moment though, I wish some of it would land so that I could send
some cleanup patches for what I think is inconsistency on top :) I
wouldn't mind if this landed as-is, it's still an improvement and the
user I mention above doesn't actually exist yet.
Reviewed-by: Conor Dooley
Cheers,
Conor.
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On Thu, May 09, 2024 at 02:56:30PM +0800, Andy Chiu wrote:
> Hi Conor,
>
> Should we check if "v" presents for vector crypto extensions in
> riscv_isa_extension_check()? We are not checking this for now. So a
> kernel compiled with RISCV_ISA_V still has a problem if its isa-string
> includes any o
On Fri, May 03, 2024 at 11:18:15AM -0700, Charlie Jenkins wrote:
> This patch series ended up much larger than expected, please bear with
> me! The goal here is to support vendor extensions, starting at probing
> the device tree and ending with reporting to userspace.
I think I've reviewed all the
is interface :)
Reviewed-by: Conor Dooley
Cheers,
Conor.
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On Fri, May 03, 2024 at 10:15:16AM -0700, Charlie Jenkins wrote:
> The DT is improperly
> formatted since it has heterogeneous vlenb entries and has V enabled,
> but since the user disabled V in the kernel skipping the warning is
> reasonable.
I wouldn't go as far as "improperly formatted", as if
On Thu, May 02, 2024 at 09:46:38PM -0700, Charlie Jenkins wrote:
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 43
>
On Wed, May 01, 2024 at 12:48:13PM -0700, Charlie Jenkins wrote:
> On Wed, May 01, 2024 at 12:37:14PM +0100, Conor Dooley wrote:
> > On Fri, Apr 26, 2024 at 02:29:21PM -0700, Charlie Jenkins wrote:
> > > The __riscv_has_extension_likely() and __riscv_has_extension_unlikely()
&g
On Wed, May 01, 2024 at 07:03:46PM +0100, Conor Dooley wrote:
> On Wed, May 01, 2024 at 10:51:38AM -0700, Charlie Jenkins wrote:
> > On Wed, May 01, 2024 at 09:44:15AM -0700, Evan Green wrote:
> > > On Fri, Apr 26, 2024 at 2:29 PM Charlie Jenkins
> > > wrote:
> &
On Wed, May 01, 2024 at 10:51:38AM -0700, Charlie Jenkins wrote:
> On Wed, May 01, 2024 at 09:44:15AM -0700, Evan Green wrote:
> > On Fri, Apr 26, 2024 at 2:29 PM Charlie Jenkins
> > wrote:
> > > + for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
> > > + const struct
On Wed, May 01, 2024 at 09:44:15AM -0700, Evan Green wrote:
> On Fri, Apr 26, 2024 at 2:29 PM Charlie Jenkins wrote:
> > +struct riscv_isa_vendor_ext_data_list {
> > + const struct riscv_isa_ext_data *ext_data;
> > + struct riscv_isainfo *per_hart_vendor_bitmap;
> > + unsigned l
On Wed, May 01, 2024 at 10:10:57AM -0700, Charlie Jenkins wrote:
> On Wed, May 01, 2024 at 12:40:38PM +0100, Conor Dooley wrote:
> > On Fri, Apr 26, 2024 at 02:29:19PM -0700, Charlie Jenkins wrote:
> > > Separate vendor extensions out into one struct per vendor
> > &g
On Fri, Apr 26, 2024 at 02:29:19PM -0700, Charlie Jenkins wrote:
> Separate vendor extensions out into one struct per vendor
> instead of adding vendor extensions onto riscv_isa_ext.
>
> Add a hidden config RISCV_ISA_VENDOR_EXT to conditionally include this
> code.
>
> The xtheadvector vendor ext
On Fri, Apr 26, 2024 at 02:29:22PM -0700, Charlie Jenkins wrote:
> Migrate xandespmu out of riscv_isa_ext and into a new Andes-specific
> vendor namespace.
Reviewed-by: Conor Dooley
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@ extern bool riscv_isa_fallback;
>
> unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
>
> +#define EXT_ALL_VENDORS 0
It's not really "all vendors", it's standard. Otherwise, this seems all
grand to me,
Reviewed-by: Conor Dooley
Cheers,
Conor.
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break;
> +#endif
> + default:
> + return false;
> + }
> +
> + if (cpu != -1)
> + bmap = cpu_bmap[cpu].isa;
> +
> + if (bit >= bmap_size)
> + return false;
> +
> + return test_bit(bit, bmap)
On Fri, Apr 26, 2024 at 02:29:19PM -0700, Charlie Jenkins wrote:
> @@ -353,6 +336,10 @@ static void __init riscv_parse_isa_string(unsigned long
> *this_hwcap, struct risc
> bool ext_long = false, ext_err = false;
>
> switch (*ext) {
> + case 'x':
> +
On Fri, Apr 26, 2024 at 02:29:19PM -0700, Charlie Jenkins wrote:
> Separate vendor extensions out into one struct per vendor
> instead of adding vendor extensions onto riscv_isa_ext.
>
> Add a hidden config RISCV_ISA_VENDOR_EXT to conditionally include this
> code.
>
> The xtheadvector vendor ext
On Fri, Apr 26, 2024 at 02:29:17PM -0700, Charlie Jenkins wrote:
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 43
>
On Mon, Apr 29, 2024 at 05:05:01PM +0200, Clément Léger wrote:
> Add parsing for Zcmop ISA extension which was ratified in commit
> b854a709c00 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
>
> Signed-off-by: Clément Léger
Reviewed-by: Conor Dooley
Cheers,
C
mbedded CPUs instead of application processors.
>
> Signed-off-by: Clément Léger
Reviewed-by: Conor Dooley
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On Tue, Apr 30, 2024 at 01:58:11PM +0200, Clément Léger wrote:
> Yeah, see what you mean. I think we also need to define if we want to
> expose all the ISA extensions in /proc/cpuinfo (ie no matter the config
> of the kernel) or not. If so, additional validate() callback would make
> sense. If we w
On Tue, Apr 30, 2024 at 09:18:47AM +0200, Clément Léger wrote:
>
>
> On 30/04/2024 00:15, Conor Dooley wrote:
> > On Mon, Apr 29, 2024 at 05:04:55PM +0200, Clément Léger wrote:
> >> Since a few extensions (Zicbom/Zicboz) already needs validation and
> >> fut
On Mon, Apr 29, 2024 at 05:04:55PM +0200, Clément Léger wrote:
> Since a few extensions (Zicbom/Zicboz) already needs validation and
> future ones will need it as well (Zc*) add a validate() callback to
> struct riscv_isa_ext_data. This require to rework the way extensions are
> parsed and split it
On Fri, Apr 26, 2024 at 01:34:19PM -0700, Charlie Jenkins wrote:
> On Fri, Apr 26, 2024 at 05:25:20PM +0100, Conor Dooley wrote:
> > On Sat, Apr 20, 2024 at 06:04:41PM -0700, Charlie Jenkins wrote:
> > > Migrate xandespmu out of riscv_isa_ext and into a new Andes-specific
>
On Fri, Apr 26, 2024 at 01:01:10PM -0700, Charlie Jenkins wrote:
> On Fri, Apr 26, 2024 at 05:19:59PM +0100, Conor Dooley wrote:
> > On Sat, Apr 20, 2024 at 06:04:40PM -0700, Charlie Jenkins wrote:
> > > @@ -163,6 +164,8 @@ void thead_errata_patch_func(struct alt_entry *be
On Sat, Apr 20, 2024 at 06:04:41PM -0700, Charlie Jenkins wrote:
> Migrate xandespmu out of riscv_isa_ext and into a new Andes-specific
> vendor namespace.
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 8cbe6e5f9c39..84760ce61e03 100644
> --- a/drivers/perf/riscv
On Fri, Apr 26, 2024 at 04:17:52PM +0100, Conor Dooley wrote:
> On Sat, Apr 20, 2024 at 06:04:36PM -0700, Charlie Jenkins wrote:
> > If vlenb is provided in the device tree, prefer that over reading the
> > vlenb csr.
> >
> > Signed-off-by: Charlie Jenkins
> >
On Sat, Apr 20, 2024 at 06:04:40PM -0700, Charlie Jenkins wrote:
> Vendor extensions are maintained in per-vendor structs (separate from
> standard extensions which live in riscv_isa). Create vendor variants for
> the existing extension helpers to interface with the riscv_isa_vendor
> bitmaps.
> T
On Sat, Apr 20, 2024 at 06:04:39PM -0700, Charlie Jenkins wrote:
> Separate vendor extensions out into one struct per vendor
> instead of adding vendor extensions onto riscv_isa_ext.
>
> Signed-off-by: Charlie Jenkins
> ---
> arch/riscv/Kconfig | 2 +
> arch/riscv/
On Sat, Apr 20, 2024 at 06:04:36PM -0700, Charlie Jenkins wrote:
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 26 +++
On Tue, Apr 23, 2024 at 02:43:17PM +0200, Clément Léger wrote:
> The Zc* standard extension for code reduction introduces new extensions.
> This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp
> are left out of this patch since they are targeting microcontrollers/
> embedded CPUs i
On Tue, Apr 23, 2024 at 02:43:16PM +0200, Clément Léger wrote:
> Since a few extensions (Zicbom/Zicboz) already needs validation and
> future ones will need it as well (Zc*) add a validate() callback to
> struct riscv_isa_ext_data. This require to rework the way extensions are
> parsed and split it
On Wed, Apr 24, 2024 at 11:13:40AM -0400, Charlie Jenkins wrote:
> On Wed, Apr 24, 2024 at 03:51:54PM +0100, Conor Dooley wrote:
> > On Wed, Apr 24, 2024 at 04:22:02PM +0200, Alexandre Ghiti wrote:
> > > Hi Charlie,
> > >
> > > On 21/04/2024 03:04, Charlie
ng the extension
> > id ext->subset_ext_ids[j] in isainfo->isa.
> >
> > Signed-off-by: Charlie Jenkins
> > Reviewed-by: Conor Dooley
> > Fixes: 0d8295ed975b ("riscv: add ISA extension parsing for scalar crypto")
> > ---
> > arch/riscv/kernel/
On Thu, Apr 04, 2024 at 12:32:48PM +0200, Clément Léger wrote:
> Add parsing for Zimop ISA extension which was ratified in commit
> 58220614a5f of the riscv-isa-manual.
>
> Signed-off-by: Clément Léger
Reviewed-by: Conor Dooley
> ---
> arch/riscv/include/asm/hwcap.h |
On Mon, Apr 22, 2024 at 01:14:26PM +0200, Clément Léger wrote:
> On 22/04/2024 11:35, Conor Dooley wrote:
> > On Mon, Apr 22, 2024 at 10:53:10AM +0200, Clément Léger wrote:
> >> On 19/04/2024 17:51, Conor Dooley wrote:
> >>> On Thu, Apr 18, 2024 at 02:42:27PM +0200, C
On Mon, Apr 22, 2024 at 10:53:04AM +0200, Clément Léger wrote:
> On 19/04/2024 17:49, Conor Dooley wrote:
> > On Thu, Apr 18, 2024 at 02:42:26PM +0200, Clément Léger wrote:
> >> As stated by Zc* spec:
> >>
> >> "As C defines the same instructions as Zca,
On Mon, Apr 22, 2024 at 10:53:10AM +0200, Clément Léger wrote:
> On 19/04/2024 17:51, Conor Dooley wrote:
> > On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
> >> The Zc* standard extension for code reduction introduces new extensions.
> >> This patch add
On Thu, Apr 18, 2024 at 02:42:25PM +0200, Clément Léger wrote:
> The Zc* spec states that:
>
> "The C extension is the superset of the following extensions:
> - Zca
> - Zcf if F is specified (RV32 only)
> - Zcd if D is specified
> As C defines the same instructions as Zca, Zcf and Zcd, the rul
On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
> The Zc* standard extension for code reduction introduces new extensions.
> This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp
> are left out of this patch since they are targeting microcontrollers/
> embedded CPUs i
On Thu, Apr 18, 2024 at 02:42:31PM +0200, Clément Léger wrote:
> Add description for the Zcmop (Compressed May-Be-Operations) ISA
> extension which was ratified in commit c732a4f39a4 ("Zcmop is
> ratified/1.0") of the riscv-isa-manual.
Acked-by: Conor Dooley
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On Thu, Apr 18, 2024 at 02:42:26PM +0200, Clément Léger wrote:
> As stated by Zc* spec:
>
> "As C defines the same instructions as Zca, Zcf and Zcd, the rule is that:
> - C always implies Zca
> - C+F implies Zcf (RV32 only)
> - C+D implies Zcd"
>
> Add additionnal validation rules to enforce t
; depends on Zca and D and finally, Zcf can not be present on rv64.
> +allOf:
> + # Zcf extension does not exists on rv64
If there's another version, "exist".
Reviewed-by: Conor Dooley
Thanks,
Conor.
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On Thu, Apr 18, 2024 at 11:41:29AM -0700, Eric Biggers wrote:
> If the RISC-V kernel ever disables V, then it should also disable everything
> that depends on V.
>
> This would be similar to how on x86, if the kernel decides to disable AVX to
> mitigate the Gather Data Sampling vulnerability, it
On Thu, Apr 18, 2024 at 07:26:00PM +0100, Conor Dooley wrote:
> On Thu, Apr 18, 2024 at 10:39:46AM -0700, Eric Biggers wrote:
> > On Thu, Apr 18, 2024 at 10:32:03AM -0700, Eric Biggers wrote:
> > > On Thu, Apr 18, 2024 at 05:53:55PM +0100, Conor Dooley wrote:
> > > >
On Thu, Apr 18, 2024 at 10:39:46AM -0700, Eric Biggers wrote:
> On Thu, Apr 18, 2024 at 10:32:03AM -0700, Eric Biggers wrote:
> > On Thu, Apr 18, 2024 at 05:53:55PM +0100, Conor Dooley wrote:
> > > > If it would be useful to do so, we should be able to enable some of the
>
On Thu, Apr 18, 2024 at 08:52:56AM -0700, Eric Biggers wrote:
> Hi Conor,
>
> On Thu, Apr 18, 2024 at 12:02:10PM +0100, Conor Dooley wrote:
> > +CC Eric, Jerry
> >
> > On Fri, Apr 12, 2024 at 02:49:03PM +0800, Andy Chiu wrote:
> > > Make has_vector take one ar
+CC Eric, Jerry
On Fri, Apr 12, 2024 at 02:49:03PM +0800, Andy Chiu wrote:
> Make has_vector take one argument. This argument represents the minimum
> Vector subextension that the following Vector actions assume.
>
> Also, change riscv_v_first_use_handler(), and boot code that calls
> riscv_v_set
ve
> the dependency by calling match_isa_ext(). This patch makes deprecated
> parser call the same function for single letter extensions.
Sure, why not..
Reviewed-by: Conor Dooley
Thanks,
Conor.
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On Fri, Apr 12, 2024 at 02:49:01PM +0800, Andy Chiu wrote:
> Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions.
>
> Signed-off-by: Andy Chiu
Technically this should be before the patch using them in the kernel,
but
Acked-by: Conor Dooley
Cheers,
Conor.
sign
/kernel/cpufeature.c
> @@ -188,6 +188,35 @@ static const unsigned int riscv_zvbb_exts[] = {
> RISCV_ISA_EXT_ZVKB
> };
>
> +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST \
> + RISCV_ISA_EXT_ZVE32X,
Not really a reason to have a list here, there's only one thing implied.
Otherwise,
Reviewed-by: Conor Dooley
Cheers,
Conor.
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roduce riscv_v_vsize to record size of Vector
> context")
> Reported-by: Conor Dooley
> Closes:
> https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/
> Signed-off-by: Andy Chiu
Reviewed-by: Conor Dooley
Cheers,
Conor.
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/*
> + * This callsite can't fail here. It cannot fail when called on
> + * the boot hart.
I am loathe to comment on this again, so
Reviewed-by: Conor Dooley
but you could just write this as "This cannot fail wh
--
From 5ed25d0f841e755b8dd4f1f6a3ea824601758d8e Mon Sep 17 00:00:00 2001
From: Conor Dooley
Date: Wed, 17 Apr 2024 14:39:36 +0100
Subject: [PATCH] dt-bindings: riscv: cpus: add a vlen register length property
Add a property analogous to the vlenb CSR so that software can detect
the vector leng
On Mon, Apr 15, 2024 at 09:12:03PM -0700, Charlie Jenkins wrote:
> @@ -351,6 +343,14 @@ static void __init riscv_parse_isa_string(unsigned long
> *this_hwcap, struct risc
> bool ext_long = false, ext_err = false;
>
> switch (*ext) {
> + case 'x':
> +
On Mon, Apr 15, 2024 at 09:11:57PM -0700, Charlie Jenkins wrote:
> This patch series ended up much larger than expected, please bear with
> me! The goal here is to support vendor extensions, starting at probing
> the device tree and ending with reporting to userspace.
btw, patches 7 to 13 (inclusi
On Tue, Apr 16, 2024 at 05:23:51PM +0200, Clément Léger wrote:
>
>
> On 16/04/2024 16:54, Conor Dooley wrote:
> > On Mon, Apr 15, 2024 at 11:10:24AM +0200, Clément Léger wrote:
> >>
> >>
> >> On 11/04/2024 13:53, Conor Dooley wrote:
> >>> O
On Mon, Apr 15, 2024 at 11:10:24AM +0200, Clément Léger wrote:
>
>
> On 11/04/2024 13:53, Conor Dooley wrote:
> > On Thu, Apr 11, 2024 at 11:08:21AM +0200, Clément Léger wrote:
> >>>> If we consider to have potentially broken isa string (ie extensions
> >&g
On Mon, Apr 15, 2024 at 08:34:05PM -0700, Charlie Jenkins wrote:
> On Sat, Apr 13, 2024 at 12:40:26AM +0100, Conor Dooley wrote:
> > On Fri, Apr 12, 2024 at 02:31:42PM -0700, Charlie Jenkins wrote:
> > > On Fri, Apr 12, 2024 at 10:27:47PM +0100, Conor Dooley wrote:
> > >
On Fri, Apr 12, 2024 at 02:31:42PM -0700, Charlie Jenkins wrote:
> On Fri, Apr 12, 2024 at 10:27:47PM +0100, Conor Dooley wrote:
> > On Fri, Apr 12, 2024 at 01:48:46PM -0700, Charlie Jenkins wrote:
> > > On Fri, Apr 12, 2024 at 07:47:48PM +0100, Conor Dooley wrote:
> > >
On Fri, Apr 12, 2024 at 02:03:48PM -0700, Charlie Jenkins wrote:
> On Fri, Apr 12, 2024 at 09:40:03PM +0100, Conor Dooley wrote:
> > On Fri, Apr 12, 2024 at 10:43:02AM -0700, Charlie Jenkins wrote:
> > > On Fri, Apr 12, 2024 at 12:49:57PM +0100, Conor Dooley wrote:
> > >
On Fri, Apr 12, 2024 at 01:48:46PM -0700, Charlie Jenkins wrote:
> On Fri, Apr 12, 2024 at 07:47:48PM +0100, Conor Dooley wrote:
> > On Fri, Apr 12, 2024 at 10:12:20AM -0700, Charlie Jenkins wrote:
> > > On Fri, Apr 12, 2024 at 11:25:47AM +0100, Conor Dooley wrote:
> > >
On Fri, Apr 12, 2024 at 01:34:43PM -0700, Charlie Jenkins wrote:
> On Fri, Apr 12, 2024 at 08:26:12PM +0100, Conor Dooley wrote:
> > On Fri, Apr 12, 2024 at 11:46:21AM -0700, Charlie Jenkins wrote:
> > > On Fri, Apr 12, 2024 at 07:38:04PM +0100, Conor Dooley wrote:
> > >
On Fri, Apr 12, 2024 at 10:43:02AM -0700, Charlie Jenkins wrote:
> On Fri, Apr 12, 2024 at 12:49:57PM +0100, Conor Dooley wrote:
> > On Thu, Apr 11, 2024 at 09:11:14PM -0700, Charlie Jenkins wrote:
> > > Create vendor variants of the existing extension helpers. If the
> > &
On Fri, Apr 12, 2024 at 10:34:28AM -0700, Charlie Jenkins wrote:
> On Fri, Apr 12, 2024 at 11:40:38AM +0100, Conor Dooley wrote:
> > On Thu, Apr 11, 2024 at 09:11:13PM -0700, Charlie Jenkins wrote:
> > > When alternatives are disabled, riscv_cpu_isa_extension_(un)likely()
&
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