[PATCHv2 05/11] EDAC, altera: Add register offset for ECC Error Clear

From: Thor Thayer In preparation for the Arria10 peripheral ECCs, a register offset from the ECC base was added to the private data structure to index to the error clear register. Since the Arria10 L2 cache ECC registers are not contiguous, a status base address was added. Signed-off-by: Thor Th

[PATCHv2 06/11] EDAC, altera: Add IRQ flags to private data struct

From: Thor Thayer In preparation for the Arria10 peripheral ECCs, irq_flags was added to the private data structure because Arria10 uses shared IRQs while Cyclone5/Arria5 have exclusive IRQs. Signed-off-by: Thor Thayer --- v2: Split large patch into smaller patches. Add irq_flags to the pri

[PATCHv2 04/11] EDAC, altera: Add register offset for ECC Error Inject

From: Thor Thayer In preparation for the Arria10 peripheral ECCs, a register offset from the ECC base was added to the private data structure to index to the error injection register. Signed-off-by: Thor Thayer --- v2: Split large patch into smaller patches. Add an ECC error inject offset t

[PATCHv2 10/11] ARM: socfpga: Enable Arria10 L2 cache ECC on startup

From: Thor Thayer Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Use DT_MACHINE to select Arria10 L2 cache function. Signed-off-by: Thor Thayer --- v2: Split into 2 separate functions selected w

[PATCHv2 09/11] EDAC, altera: Addition of Arria10 L2 Cache ECC

From: Thor Thayer Addition of the Arria10 L2 Cache ECC handling. Addition of private data structure for Arria10 L2 cache ECC and the initialization function for it. Signed-off-by: Thor Thayer --- v2: Split large patch into smaller patches. Addition of Arria10 L2 cache dependency check and p

[PATCHv3 1/9] EDAC: Altera L2 Kconfig change from select to depends upon.

From: Thor Thayer Force L2 cache dependency instead of forcing selection of L2 cache. Signed-off-by: Thor Thayer --- v2/3 No change --- drivers/edac/Kconfig |5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 37755e6..6c

[PATCHv3 2/9] EDAC, altera: Move Device structs and defines to header file

From: Thor Thayer Move the device structs and defines to altera_edac.h in preparation for adding the Arria10 L2 cache ECC. Signed-off-by: Thor Thayer --- v2: Split original patch into smaller patches. Move private data and defines into header file. v3: Commented description above defines. -

[PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

From: Thor Thayer Add the device tree entries needed to support the Altera L2 cache EDAC on the Arria10 chip. Signed-off-by: Thor Thayer --- v2 Match register value (l2-ecc@ffd06010) v3 Set ecc_manager to beginning of system_manager. Add sysman phandle. Move IRQs into ecc_manager from childr

[PATCHv3 7/9] EDAC, altera: Addition of Arria10 L2 Cache ECC

From: Thor Thayer Addition of the Arria10 L2 Cache ECC handling. Addition of private data structure for Arria10 L2 cache ECC and the probe function for it. The Arria10 ECC device IRQs are in a shared register so the ECC Manager parent/child relationship requires a different probe function. Signe

[PATCHv3 8/9] ARM: socfpga: Enable Arria10 L2 cache ECC on startup

From: Thor Thayer Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Use DT_MACHINE to select Arria10 L2 cache function. Signed-off-by: Thor Thayer Acked-by: Dinh Nguyen --- v2: Split into 2 separa

[PATCHv3 5/9] EDAC, altera: Add register offset for ECC Error Inject

From: Thor Thayer In preparation for the Arria10 peripheral ECCs, a register offset from the ECC base was added to the private data structure to index to the error injection register. Signed-off-by: Thor Thayer --- v2: Split large patch into smaller patches. Add an ECC error inject offset t

[PATCHv3 4/9] EDAC, altera: Abstract ECC Enable Mask in check_deps()

From: Thor Thayer In preparation for the Arria10 peripheral ECCs, the ECC Enable mask is used in place of hard coded masks in the check dependency functions. Signed-off-by: Thor Thayer --- v3: This change added. --- drivers/edac/altera_edac.c |9 +++-- 1 file changed, 7 insertions(+),

[PATCHv3 3/9] EDAC, altera: Remove platform device from check_deps()

From: Thor Thayer In preparation for the Arria10 peripheral ECCs, the platform device parameter is removed from the check_deps() functions because it is not needed and makes the Arria10 check_deps() cleaner. Signed-off-by: Thor Thayer --- v3: This change added. --- drivers/edac/altera_edac.c

[PATCHv3 6/9] Documentation: dt: socfpga: Add Altera Arria10 L2 cache binding

From: Thor Thayer Add the device tree bindings needed to support the Altera L2 cache on the Arria10 chip. Since all the peripherals share IRQs, the IRQ fields are now in the ecc_manager. Signed-off-by: Thor Thayer --- v2 Correct spelling of Arria10 in patch title. v3 Major restructuring change

Series adding Arria10 L2 Cache EDAC

This version refactors how the EDAC is configured for Arria10 since the ECC hardware is significantly different than Cyclone5 and Arria5. Since all the IRQs are shared, a new probe function based on the xgene codebase was used. [PATCHv3 1/9] EDAC: Altera L2 Kconfig change from select to depends [

[PATCHv10 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer --- v10: Changes noted by maintainer included: F

[PATCHv10 2/4] ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries

From: Thor Thayer Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly. http://www.spinics.net/lists/devicetree/msg51117.html Signed-off-by: Thor Thayer Acked-by:

[PATCHv10 3/4] ARM: socfpga: enable L2 cache ECC on startup

From: Thor Thayer This patch enables the ECC for L2 cache on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Signed-off-by: Thor Thayer Acked-by: Dinh Nguyen --- v10: No change v9: Improve node put handling. v8: Address communi

[PATCHv10 4/4] ARM: socfpga: Enable OCRAM ECC on startup

From: Thor Thayer This patch enables the ECC for On-Chip RAM on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Signed-off-by: Thor Thayer Acked-by: Dinh Nguyen --- v10: No change v9: Improve node release handling. v8: Address

[PATCH 1/5] EDAC: Altera L2 Kconfig change from select to depends upon.

From: Thor Thayer Force L2 cache dependency instead of forcing selection of L2 cache. Signed-off-by: Thor Thayer --- drivers/edac/Kconfig |5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 37755e6..6ca7474 100644 --- a/

[PATCH 4/5] ARM: socfpga: Enable Arria10 L2 cache ECC on startup

From: Thor Thayer Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Signed-off-by: Thor Thayer --- arch/arm/mach-socfpga/l2_cache.c | 42 ++ 1 file changed, 3

[PATCH 3/5] EDAC, altera: Addition of Arria10 L2 Cache ECC

From: Thor Thayer Addition of the Arria10 L2 Cache ECC handling. The major changes affect the L2 ECC registers not being grouped together. The Arria10 IRQ status needs to be mapped into a different region. The mapping occurs in the L2 specific function. Important changes include: 1) Move private

[PATCH 2/5] Documentation: dt: socfpga: Add Altera Arri10 L2 cache binding

From: Thor Thayer Add the device tree binding string needed to support the Altera L2 cache on the Arria10 chip. Signed-off-by: Thor Thayer --- .../bindings/arm/altera/socfpga-eccmgr.txt |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bi

[PATCH 5/5] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

From: Thor Thayer Add the device tree entries needed to support the Altera L2 cache EDAC on the Arria10 chip. Signed-off-by: Thor Thayer --- arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/ar

[PATCHv9 4/4] ARM: socfpga: Enable OCRAM ECC on startup

From: Thor Thayer This patch enables the ECC for On-Chip RAM on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Signed-off-by: Thor Thayer --- v9: Improve node release handling. v8: Address community comments on strings. Fix match

[PATCHv9 2/4] ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries

From: Thor Thayer Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly. http://www.spinics.net/lists/devicetree/msg51117.html Signed-off-by: Thor Thayer Acked-by:

[PATCHv9 3/4] ARM: socfpga: enable L2 cache ECC on startup

From: Thor Thayer This patch enables the ECC for L2 cache on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Signed-off-by: Thor Thayer --- v9: Improve node put handling. v8: Address community suggestions for strings. Fix string b

[PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer --- v9: Improve device tree node release. Free m

[PATCH 0/4] Add Altera A10SR Status & Control Monitor

From: Thor Thayer This patch series adds the Altera Arria10 DevKit System Resource chip's Status and Control Monitor to the A10SR Multi-Function Device. An earlier patch added this to the hwmon class which wasn't the proper place so this functionality is added to the misc directory. Thor Thayer

[PATCH 4/4] ARM: socfpga: dts: Add Monitor to A10-SR MFD

From: Thor Thayer Add the Monitor functionality to the Arria10 DevKit System Resource chip. Signed-off-by: Thor Thayer --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |4 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/s

[PATCH 1/4] dt-bindings: mfd: Add Altera Arria10 SR Monitor

From: Thor Thayer Add the Arria10 DevKit System Resource Chip register and state monitoring module to the MFD. Signed-off-by: Thor Thayer --- Note: This needs to be applied to the bindings document that was Acked & Applied but didn't reach the for-next branch. See https://patchwork.ozlabs.org/p

[PATCH 3/4] mfd: altr-a10sr: Add Arria10 SR Monitor

From: Thor Thayer Add the Altera Arria10 DevKit System Resource Monitor functionality to the MFD device. Signed-off-by: Thor Thayer --- drivers/mfd/altera-a10sr.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c index 06e1f7f..0

[PATCH 2/4] misc: Add Altera Arria10 System Resource Control

From: Thor Thayer This patch adds the Altera Arria10 control & monitoring functions to the Arria10 System Resource chip. Signed-off-by: Thor Thayer --- MAINTAINERS |1 + drivers/misc/Kconfig|7 ++ drivers/misc/Makefile |1 + drivers/misc/al

[PATCH] EDAC, altera: Disable IRQ while injecting SDRAM errors

From: Thor Thayer Disable IRQs while injecting SDRAM errors. The RT patches exposed a spinlock deadlock where the spinlock taken for the regmap write deadlocked with the IRQ clear regmap write. Error injection is not normally enabled for ECC but only for testing. Signed-off-by: Thor Thayer ---

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