From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Add interrupts for SBERR and DBERR.
v4 No change
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 16
1 fil
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Move them outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
v2 New patch. Move shared functions outside OCRAM only area.
v3 C
From: Thor Thayer
The device private data structures should be converted from const
struct edac_device_prv_data to static const struct edac_device_prv_data.
Signed-off-by: Thor Thayer
---
v4 New patch added for conversion.
---
drivers/edac/altera_edac.c | 16
1 file changed
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.
Signed-off-by: Thor Thayer
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific func
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors.
OCRAM uncorrectable errors cause a panic because sleep/resume
functions and FPGA contents during sleep are stored in OCRAM.
ECCs on peri
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No Change
v3 Change to common compatible string based on maintainer comments
Add local IRQ values.
v4 Add compatible string for parent
From: Thor Thayer
This patch set adds the Ethernet EDAC and memory initialization functions
for Altera's Arria10 peripherals. The ECC memory init functions are common
to all the peripheral memory buffers (to follow in later patches).
Thor Thayer (7):
EDAC, altera: Add panic flag check to A10 I
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all ethernet
FIFOs in the DT.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
From: Thor Thayer
Initialize the tx_loadsz parameter from passed in devicetree
tx-threshold parameter.
The tx_loadsz is calculated as the number of bytes to fill FIFO
when tx-threshold is triggered.
Signed-off-by: Thor Thayer
---
v2 Change from reading tx-loadsz parameter to reading
tx-thr
From: Thor Thayer
The tx-threshold parameter sets the TX FIFO low water threshold
trigger for the Altera 16550-FIFO32 soft IP.
Signed-off-by: Thor Thayer
---
v2 Change from tx-loadsz to tx-threshold
---
arch/nios2/boot/dts/10m50_devboard.dts |1 +
1 file changed, 1 insertion(+)
diff --g
From: Thor Thayer
Some variants of the 16550 have a programmable TX FIFO threshold that
will trigger an IRQ when the FIFO drops below the threshold. The Altera
16550 compatible soft IP supports programmable TX FIFO thresholds.
This patch series adds the tx-threshold parameter to the device tree.
From: Thor Thayer
Add the device tree binding needed to support the TX FIFO threshold
parameter.
Signed-off-by: Thor Thayer
---
v2 Change parameter name from tx-loadsz to tx-threshold
---
Documentation/devicetree/bindings/serial/8250.txt |2 ++
1 file changed, 2 insertions(+)
diff --git
From: Thor Thayer
The Altera 16550 soft IP UART requires 2 additional registers for
TX FIFO threshold support. These 2 registers enable the TX FIFO
Low Watermark and set the TX FIFO Low Watermark.
Set the TX FIFO threshold to the FIFO size - tx_loadsz.
Signed-off-by: Thor Thayer
---
v2 Add bou
From: Thor Thayer
Correct the error message sent out in the case of a single
bit error IRQ allocation.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index
From: Thor Thayer
Add the IRQF_ONESHOT and IRQF_TRIGGER_HIGH flags to disable the
IRQ while executing the IRQ handler. Remove the IRQF_SHARED because
these are not shared IRQs in the domain. Exposed when flooding IRQs.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 18 ++
From: Thor Thayer
Some variants of the 16550 have a programmable TX FIFO threshold that
will trigger an IRQ when the FIFO drops below the threshold. The Altera
16550 compatible soft IP supports programmable TX FIFO thresholds.
This patch series adds the tx_loadsz to the device tree. The tx_loads
From: Thor Thayer
The tx-loadsz parameter sets the TX FIFO threshold level of
the Altera 16550-FIFO32 soft IP.
Signed-off-by: Thor Thayer
---
arch/nios2/boot/dts/10m50_devboard.dts |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/nios2/boot/dts/10m50_devboard.dts
b/arch/nios2/boot/
From: Thor Thayer
The Altera 16550 soft IP UART requires 2 additional registers for
TX FIFO threshold support. These 2 registers enable the TX FIFO
Low Watermark and set the TX FIFO Low Watermark.
These registers are initialized in serial8350_do_startup(). Set
the TX FIFO threshold to the FIFO si
From: Thor Thayer
Add the device tree bindings needed to support the TX FIFO
load size.
Signed-off-by: Thor Thayer
---
Documentation/devicetree/bindings/serial/8250.txt |1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/8250.txt
b/Documentation/dev
From: Thor Thayer
Initialize the tx_loadsz parameter if it is defined in the
device tree.
Signed-off-by: Thor Thayer
---
drivers/tty/serial/8250/8250_of.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_of.c
b/drivers/tty/serial/8250/8250_of.c
index 3
From: Thor Thayer
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
---
v2: Split OCRAM initialization into separate patch.
v3/4: No change
v5: Remove l2cac
From: Thor Thayer
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
Signed-off-by: Thor Thayer
---
v2: R
From: Thor Thayer
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
v2 changes:
- Split On-Chip RAM ECC platform initialization into separate patch from
L2 ECC pl
From: Thor Thayer
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
---
v2: Split OCRAM ECC portion separately. Addition of iounmap()
and reorganizatio
From: Thor Thayer
The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.
Signed-off-by: Thor Thayer
---
v3: Added in this version as a separate patch.
v4-6: No change.
---
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
Each type of ECC is individually configurable.
The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation
From: Thor Thayer
This series of patches adds support for the Arria10 EDAC. The
SDRAM controller and ECC registers are significantly different
from the CycloneV/ArriaV but common areas could be abstracted.
Thor Thayer (4):
edac, altera: Generalize driver to use DT Memory size
edac, altera: R
From: Thor Thayer
Support for the Arria10 SDRAM EDAC is added to the device tree.
Update the bindings document for the new match string.
Signed-off-by: Thor Thayer
---
v2: Change subject description format.
---
.../bindings/arm/altera/socfpga-sdram-edac.txt |2 +-
arch/arm/boot/dts/soc
From: Thor Thayer
The Arria10 SDRAM and ECC system differs significantly from the
Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10
SoC.
1) IRQ handler needs to support SHARED IRQ
2) Support sberr and dberr address reporting.
Signed-off-by: Thor Thayer
---
v2: Reposition a10_unm
From: Thor Thayer
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs in preparation for the Arria10 support.
Signed-off-by: Thor Thayer
---
v2: Make c5_data static.
---
drivers
From: Thor Thayer
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. The memory size is calculated in
the bootloader and passed via the device tree. Using this device
tree size is more generic than using the register fields to
calculate the mem
From: Thor Thayer
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer
To: Rob Herring
To: Pawel Moll
To: Mark Rutland
To: Ian Campbell
To: Kumar Gala
To: Rob Landley
To: Russell King
To: Dinh Nguyen
Cc: devicet...@vger
From: Thor Thayer
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer
To: Rob Herring
To: Pawel Moll
To: Mark Rutland
To: Ian Campbell
To: Kumar Gala
To: Rob Landley
To: Russell King
To: Dinh Nguyen
Cc: devicet..
From: Thor Thayer
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC framework
is discov
From: Thor Thayer
The Altera SDRAM controller and EDAC support are added in this
patch series. The SDRAM controller is an MFD so that multiple
drivers can access it's registers.
Thor Thayer (3):
mfd: altera: Add Altera SDRAM Controller
edac: altera: Add Altera EDAC support.
arm: dts: Add A
From: Thor Thayer
Add a simple MFD for the Altera SDRAM Controller.
Signed-off-by: Alan Tull
Signed-off-by: Thor Thayer
---
v1-8: The MFD implementation was not included in the original series.
v9: New MFD implementation.
---
MAINTAINERS|5 ++
drivers/mfd/Kconfig
From: Thor Thayer
Add the Altera SDRAM controller bindings and device tree changes to the Altera
SoC project.
Signed-off-by: Thor Thayer
---
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Chang
From: Thor Thayer
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maint
[PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv5 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv5 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to m
From: Thor Thayer
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
Signed-off-by: Thor Thayer
---
.../bindings/arm/a
From: Thor Thayer
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.
v3: EDAC driver cleanup based on comments from Mailing list.
v4: Panic on DBE. Add macro around inject-error reads to prevent
From: Thor Thayer
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Change, bump version for consi
From: Thor Thayer
This patch adds EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controllers.
- The SDRAM Controller registers are shared with the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC
From: Thor Thayer
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
Signed-off-by: Thor Thayer
---
.../
From: Thor Thayer
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4: No changes - bump version for consistency.
Signed-off-by: Thor Thayer
---
.../bindings/arm/alte
[PATCHv4 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv4 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv4 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a
From: Thor Thayer
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
---
v2: Update the mailing list to include the EDAC mailing list.
Signed-off-by: Thor Thayer
To: Rob Herring
To: Pawel Moll
To: Mark Rutland
To: Ian Campbell
To: Kumar Gala
To:
From: Thor Thayer
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC framework
is discov
From: Thor Thayer
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
---
v2: Update the mailing list to include the EDAC mailing list.
Signed-off-by: Thor Thayer
To: Rob Herring
To: Pawel Moll
To: Mark Rutland
To: Ian Campbell
To: Kumar Gala
[PATCHv6 1/3] dt: bindings: Addition of the Altera SDRAM controller
[PATCHv6 2/3] dt: bindings: Addition of the Altera SDRAM EDAC
[PATCHv6 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
From: Thor Thayer
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Change, bump version for consistency.
v6: Only map the ctrlcfg register as syscon.
Signed-off-by: Thor Thayer
---
.../bindings/
From: Thor Thayer
Addition of the Altera SDRAM controller to the EDAC driver.
Thor Thayer (3):
Addition of the Altera SDRAM controller bindings and device tree
changes to the Altera SoC project.
Addition of the Altera SDRAM EDAC bindings and device tree
changes to the Altera
From: Thor Thayer
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
v6: Assign ECC registers in SDRAM controller to EDAC
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-sdram-edac.txt | 15 +
From: Thor Thayer
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.
v3: EDAC driver cleanup based on comments from Mailing list.
v4: Panic on DBE. Add macro around inject-error reads to prevent
From: Thor Thayer
Addition of the Altera SDRAM EDAC bindings and device tree changes
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
v6: Assign ECC registers in SDRAM controller to EDAC
Signed-off-by: Thor Thay
From: Thor Thayer
Addition of the driver to support the Altera SDRAM Controller.
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tre
From: Thor Thayer
Addition of the Altera SDRAM Controller bindings and device tree changes.
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Change, bump version for consistency.
v6: Only map the
From: Thor Thayer
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add main
From: Thor Thayer
Thor Thayer (3):
devicetree: Addition of the Altera SDRAM Controller. Add the
Altera SDRAM controller bindings and device tree changes to the
Altera SoC project.
devicetree: Addition of the Altera SDRAM EDAC. Add the Altera
SDRAM EDAC bindings and dev
From: Thor Thayer
Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer
---
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
v6: Assign ECC registers in SDRAM c
From: Thor Thayer
Add the Altera SDRAM controller bindings and device tree changes to the Altera
SoC project.
Signed-off-by: Thor Thayer
---
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Chang
From: Thor Thayer
The D_CAN driver was written to support the TI D_CAN implementation
which placed the D_CAN RAM reset in a separate register. In the
standard D_CAN module the RAM Init is in the D_CAN module so
handle the RAM Init differently.
This patch has only been tested on the standard D_CAN
The standard D_CAN module includes the RAM Init bit in one of the
D_CAN registers. This patch will properly initialize the RAM Init
bit which is self-clearing when the RAM Init is complete.
This patch fixes a boot message reporting an invalid resource as
well as the message saying control memory i
From: Thor Thayer
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer
To: Rob Herring
To: Pawel Moll
To: Mark Rutland
To: Ian Campbell
To: Kumar Gala
To: Rob Landley
To: Russell King
To: Dinh Nguyen
Cc: devicet..
From: Thor Thayer
Addition of the Altera SDRAM controller registers to the
Altera SoC project. These registers are shared by future
drivers such as ECC and the FPGA bridge.
Signed-off-by: Thor Thayer
To: Rob Herring
To: Pawel Moll
To: Mark Rutland
To: Ian Campbell
To: Kumar Gala
To: Rob La
From: Thor Thayer
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
---
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-sdram-edac.txt | 12
This patch adds EDAC support for the Altera CycloneV and ArriaV
SoC SDRAM Controller.
[PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv3 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM
--
To unsubscribe fro
From: Thor Thayer
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project. The "syscon" parameter
is included here because the SDRAM EDAC bits are shared with the SDRAM
configuration bits.
---
v2: Changes to SoC SDRAM EDAC code.
V3: Implement code sugge
From: Thor Thayer
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.
v3: EDAC driver cleanup based on comments from Mailing list.
Signed-off-by: Thor Thayer
---
MAINTAINERS|
From: Thor Thayer
This patch series adds Altera SDRAM EDAC support.
The one sticky issue seems to be the use of "syscon". One register
in the SDRAM controller shares bitfields with different functionality.
In this series the devicetree includes the "syscon" designation
for the SDRAM Controller [
From: Thor Thayer
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor Thayer
---
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
v6: Assign ECC registers i
From: Thor Thayer
Add the Altera SDRAM controller bindings and device tree changes to the Altera
SoC project.
Signed-off-by: Thor Thayer
---
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Chang
From: Thor Thayer
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add main
From: Thor Thayer
The Altera SDRAM controller EDAC support is added in this
patch series. The SDRAM controller shares its registers with
the EDAC, and 2 upcoming drivers (fpga bridge and power control).
This series of patches started using the syscon driver to share
the SDRAM controller registers
From: Thor Thayer
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maint
From: Thor Thayer
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor Thayer
---
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Change, bum
From: Thor Thayer
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
v2 changes:
- Split On-Chip RAM ECC platform initialization into separate patch from
L2 ECC pl
From: Thor Thayer
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
---
v2: Split OCRAM ECC portion separately. Addition of iounmap()
and reorganization of
From: Thor Thayer
The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.
Signed-off-by: Thor Thayer
---
v3: Added in this version as a separate patch.
---
drivers/edac/Kcon
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model. All
Altera EDAC functions live in altera_edac.c.
Signed-off-by: Thor Thayer
---
v2: Fix L2 dependency comments.
v3: Move O
From: Thor Thayer
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
Signed-off-by: Thor Thayer
---
v2: R
From: Thor Thayer
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
---
v2: Split OCRAM initialization into separate patch.
v3: No change
---
MAINTAINERS
From: Thor Thayer
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
v2 changes:
- Split On-Chip RAM ECC platform initialization into separate patch from
L2 ECC pl
From: Thor Thayer
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
---
v2: Split OCRAM initialization into separate patch.
v3/4: No change
---
MAINTAINERS
From: Thor Thayer
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
---
v2: Split OCRAM ECC portion separately. Addition of iounmap()
and reorganization of
From: Thor Thayer
The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.
Signed-off-by: Thor Thayer
---
v3: Added in this version as a separate patch.
v4: No change.
---
d
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation can take almost 2 seconds on boot and some
cust
From: Thor Thayer
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
Signed-off-by: Thor Thayer
---
v2: R
From: Thor Thayer
The Arria10 IRQs for each peripheral ECC block funnel into 2 IRQs
[1 for single bit errors (SBERR) and 1 for double bit errors (DBERR)]
which are better handled by the IRQ controller and IRQ domain
framework than the IRQ handler in the current implementation.
The IRQ numbers (h
From: Thor Thayer
To better support child devices, the ECC manager needs to be
implemented as an IRQ controller.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 162 +---
drivers/edac/altera_edac.h |5 +-
2 files changed, 125 insertions(
From: Thor Thayer
Changes to support ECC Manager as SDRAM IRQ parent by
1) updating IRQ property values to correct child IRQs
2) moving node under ECC Manager.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 13 +++--
1 file changed, 7 insertions(+), 6 deletio
From: Thor Thayer
Changes to support IRQ controller implementation including adding
new property irq-controller to eccmgr and adding IRQ property
to children.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch
From: Thor Thayer
Designate the ECC Manager as an interrupt controller and add child
interrupts.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindi
From: Thor Thayer
Separate the device match arrays for each platform to prevent
CycloneV matches when calling of_platform_populate() on the
Arria10 ECC manager node.
If the SDRAM is a child node of ECC manager, call probe function
via of_platform_populate().
Signed-off-by: Thor Thayer
---
driv
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
Each type of ECC is individually configurable.
Signed-off-by: Thor Thayer
Signed-off-by: Dinh Nguyen
---
v8: Remove MASK
From: Dinh Nguyen
This patch enables the ECC for On-Chip RAM on machine startup. The ECC
has to be enabled before data is stored in memory otherwise the ECC will
fail on reads.
Signed-off-by: Thor Thayer
Signed-off-by: Dinh Nguyen
---
v8: Address community comments on strings. Fix match string
From: Thor Thayer
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
Signed-off-by: Thor Thayer
Signed-of
From: Dinh Nguyen
This patch enables the ECC for L2 cache on machine startup. The ECC has to
be enabled before data is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
Signed-off-by: Dinh Nguyen
---
v8: Address community suggestions for strings. Fix string base
From: Thor Thayer
debugfs_remove() is used to remove a file or a directory from the
debugfs filesystem on an EDAC device exit. However edac_debugfs
might not be empty. This is similar to another patch [1] that
changed the EDAC MCI code to use edac_debugfs_remove_recursive().
[1] https://lkml.org
From: Thor Thayer
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
---
v2: Split OCRAM initialization into separate patch.
v3/4: No change
v5: Remove l2cac
1 - 100 of 234 matches
Mail list logo
