> > don't start a distribution while one is already running. However, even
> > in the event that this race occurs, it is fine to have two distributions
> > running (especially now that distribute grabs the cfs_b->lock to
> > determine remaining quota before assigning).
> &g
a possibility for it. However:
> >
> > "Cpusets provide a Linux kernel mechanism to constrain which CPUs and
> > Memory Nodes are used by a process or set of processes.
> >
> > The Linux kernel already has a pair of mechanisms to specify on which
> > CPUs a task may be scheduled (sched_setaffinity) and on which Memory
> > Nodes it may obtain memory (mbind, set_mempolicy).
> >
> > Cpusets extends these two mechanisms as follows:"
> >
> > The isolation flags do not necessarily have anything to do with
> > tasks, but with CPUs: a given feature is disabled or enabled on a
> > given CPU.
> > No?
>
> One cpumask per feature, implemented separately in sysfs, also
> seems OK (modulo documentation about the RCU update and users
> of the previous versions).
>
> This is what is being done for rcu_nocbs= already...
>
exclusive cpusets is used now to control scheduler load balancing on
a group of cpus. It seems to me that this is the same idea and is part
of the isolation concept. Having a toggle for each subsystem/feature in
cpusets could provide the needed userspace api.
Under the covers it might be implemented as twiddling various cpumasks.
We need to be shifting to managing load balancing with cpusets anyway.
Cheers,
Phil
--
On Wed, Sep 02, 2020 at 12:44:42PM +0200 Dietmar Eggemann wrote:
> + Phil Auld
>
Thanks Dietmar.
> On 28/08/2020 19:26, Qais Yousef wrote:
> > On 08/28/20 19:10, Dietmar Eggemann wrote:
> >> On 28/08/2020 12:27, Qais Yousef wrote:
> >>> On 08/28/20 10
Hi Quais,
On Mon, Sep 07, 2020 at 12:02:24PM +0100 Qais Yousef wrote:
> On 09/02/20 09:54, Phil Auld wrote:
> > >
> > > I think this decoupling is not necessary. The natural place for those
> > > scheduler trace_event based on trace_points extension files is
&g
>> this patch allowing the arm64 DMA zone be configurable.
>>
>> Signed-off-by: Alix Wu
>> Signed-off-by: YJ Chiang
>> Signed-off-by: Phil Chang
>> ---
>> Hi
>>
>> For some devices, the main memory split into 2 part due to the memory
ee to advise on any corrections or improvements that can be
> made.
Thanks for these. I wonder, though, if it would not make more sense
to post these changes as comments on the original as-yet-unmerged
patches that you are fixing up?
Cheers,
Phil
>
> John B. Wyatt IV (8):
> sched
erally equivalent to SLAB in terms of performance. Block
> > multiqueue also had vaguely similar issues before the default changes
> > and a period of time before it was removed removed (example whinging mail
> > https://lore.kernel.org/lkml/20170803085115.r2jfz2lofy5sp...@techsingularity.net/)
> > It's schedutil's turn :P
> >
>
Agreed. I'd like the option to switch back if we make the default change.
It's on the table and I'd like to be able to go that way.
Cheers,
Phil
--
ault resulting in unfair finger pointing at one company's test
> team. If at least two distos check it out and it still goes wrong, at
> least there will be shared blame :/
>
> > > Other distros assuming they're watching can nominate their own victim.
> >
> >
> @@ -5105,9 +5105,6 @@ static void do_sched_cfs_slack_timer(struct
> cfs_bandwidth *cfs_b)
> return;
>
> distribute_cfs_runtime(cfs_b);
> -
> - raw_spin_lock_irqsave(&cfs_b->lock, flags);
> - raw_spin_unlock_irqrestore(&cfs_b->lock, flags);
> }
>
> /*
> --
> 2.29.0
>
>
Nice :)
Reviewed-by: Phil Auld
--
How are you doing today I have a proposal which i think may interest you and
benefit you.I will like to give you full details of this via email:
gerradfinancialplann...@gmail.com
Thanks.
John PHIL
hackbench latency on the same EPYC
first gen servers.
As I mentioned earlier in the thread we have all the 5.9 patches in this area
in our development distro kernel (plus a handful from 5.10-rc) and don't see
the same effect we see here between 5.8 and 5.9 caused by this patch. But
there are other variables there. We've queued up a comparison between that
kernel and one with just the patch in question reverted. That may tell us
if there is an effect that is otherwise being masked.
Jirka - feel free to correct me if I mis-summarized your results :)
Cheers,
Phil
--
On Mon, Nov 09, 2020 at 03:38:15PM + Mel Gorman wrote:
> On Mon, Nov 09, 2020 at 10:24:11AM -0500, Phil Auld wrote:
> > Hi,
> >
> > On Fri, Nov 06, 2020 at 04:00:10PM + Mel Gorman wrote:
> > > On Fri, Nov 06, 2020 at 02:33:56PM +0100, Vincent Guittot wrote:
;
raw_spin_unlock_irqrestore(&cfs_b->lock, flags);
It's just a leftover. I agree that if it was there for some other
purpose that it would really need a comment. In this case, it's an
artifact of patch-based development I think.
Cheers,
Phil
> avid
>
> -
> Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1
> 1PT, UK
> Registration No: 1397386 (Wales)
>
--
e load balancing improvements and some minor overall perf
gains in a few places, but generally did not see any difference from before
the commit mentioned here.
I'm wondering, Mel, if you have compared 5.10-rc1?
We don't have everything though so it's possible something we have
n
ance threshold
> > sched/fair: minimize concurrent LBs between domain level
> > sched/fair: reduce busy load balance interval
>
> I see nothing objectionable there, a little more testing can't hurt, but
> I'm tempted to apply them.
>
> Phil, Mel, any chance
Actually, In a embedded system with 3GB memory, the memory bus width is not the
same among the 3GB.
(The first 2GB is 48-bit wide, and the latter 1GB is 16-bit wide.)
For memory throughput reason of hardware IPs, we need allocate memory from the
first 2GB for
the hardware IPs. And that is why we
On Thu, Sep 24, 2020 at 09:37:33AM -0700 Tim Chen wrote:
>
>
> On 9/22/20 12:14 AM, Vincent Guittot wrote:
>
> >>
>
> And a quick test with hackbench on my octo cores arm64 gives for 12
>
> Vincent,
>
> Is it octo (=10) or octa (=8) cores on a single socket for your system?
In what
On Thu, Sep 24, 2020 at 10:43:12AM -0700 Tim Chen wrote:
>
>
> On 9/24/20 10:13 AM, Phil Auld wrote:
> > On Thu, Sep 24, 2020 at 09:37:33AM -0700 Tim Chen wrote:
> >>
> >>
> >> On 9/22/20 12:14 AM, Vincent Guittot wrote:
> >>
> >>>
inimal imbalance threshold
> > sched/fair: minimize concurrent LBs between domain level
> > sched/fair: reduce busy load balance interval
>
> I see nothing objectionable there, a little more testing can't hurt, but
> I'm tempted to apply them.
>
> Phil,
On Fri, Sep 18, 2020 at 12:39:28PM -0400 Phil Auld wrote:
> Hi Peter,
>
> On Mon, Sep 14, 2020 at 01:42:02PM +0200 pet...@infradead.org wrote:
> > On Mon, Sep 14, 2020 at 12:03:36PM +0200, Vincent Guittot wrote:
> > > Vincent Guittot (4):
> > > sched/fair: relax
,
> gfp_zone(GFP_HIGHUSER),
> @@ -2516,6 +2520,7 @@ int mpol_misplaced(struct page *page, struct
> vm_area_struct *vma, unsigned long
>
> /* Migrate the page towards the node whose CPU is referencing it */
> if (pol->flags & MPOL_F_MORON) {
> +moron:
> polnid = thisnid;
>
> if (!should_numa_migrate_memory(current, page, curnid, thiscpu))
> --
> 2.28.0
>
Cheers,
Phil
--
Allowing the DMA32 zone be configurable in ARM64 but at most 4Gb.
Signed-off-by: Alix Wu
Signed-off-by: YJ Chiang
Signed-off-by: Phil Chang
---
.../admin-guide/kernel-parameters.txt | 3 ++
arch/arm64/include/asm/memory.h | 2 +
arch/arm64/mm/init.c
this patch allowing the DMA32 zone be configurable in ARM64.
Signed-off-by: Alix Wu
Signed-off-by: YJ Chiang
Signed-off-by: Phil Chang
---
For some devices, the main memory split into 2 part due to the memory
architecture, the efficient and less inefficient part.
One of the use case is fine
of architecture
Signed-off-by: Alix Wu
Signed-off-by: YJ Chiang
Signed-off-by: Phil Chang
---
Hi
supplement the reason of this usage.
Thanks.
.../admin-guide/kernel-parameters.txt | 3 +++
arch/arm64/include/asm/memory.h | 2 ++
arch/arm64/mm/init.c
to also back-port [2] to 4.19, but that leaves open the
question of
whether either the overlay application mechanism or the unit test framework
should have
detected the missing phandle.
Phil
[1] 8814dc46bd9e ("of: overlay: do not duplicate properties from overlay for
new nodes")
[2] f
Hi Frank,
On 04/06/2019 19:20, Frank Rowand wrote:
Hi Phil,
On 6/4/19 5:15 AM, Phil Elwell wrote:
Hi,
In the downstream Raspberry Pi kernel we are using configfs to apply overlays at
runtime, using a patchset from Pantelis that hasn't been accepted upstream yet.
Apart from the occas
the kernel just fine in cgroup v2. A user who wishes
> for the previous affinity mask to be restored in this fallback case can use
> that mechanism instead.
>
> This patch modifies scheduler behavior by instead resetting the mask to
> task_cs(tsk)->cpus_allowed by default, and cpu_pos
io controller, i2c controller, gmac, dmac, Arasan sdio controller). The
commit to add this clock to the i2c controller driver is my fault, as I was
following the pattern of the others.
Of the few drivers that don't already get the hclk/pclk used to access the
peripherals is the Synopsys spi
Hi Geert,
On 03 June 2019 09:39 Geert Uytterhoeven wrote:
> On Mon, Jun 3, 2019 at 10:29 AM Phil Edworthy wrote:
> > On 28 May 2019 08:29 Geert Uytterhoeven wrote:
> > > On Fri, May 24, 2019 at 5:32 PM Gareth Williams wrote:
> > > > The driver is gaining power
first loop.
Address this issue by saving the se pointer when the first loop exits and
resetting it before doing the fix up, if needed.
Signed-off-by: Phil Auld
Cc: Peter Zijlstra (Intel)
Cc: Vincent Guittot
Cc: Ingo Molnar
Cc: Juri Lelli
---
kernel/sched/fair.c | 4
1 file changed, 4 insertion
Hi Vincent,
Thanks for taking a look. More below...
On Wed, May 06, 2020 at 06:36:45PM +0200 Vincent Guittot wrote:
> Hi Phil,
>
> - reply to all this time
>
> On Wed, 6 May 2020 at 16:18, Phil Auld wrote:
> >
> > sched/fair: Fix enqueue_task_fair warning some mo
acepoints are added to add_nr_running() and sub_nr_running() which
are in kernel/sched/sched.h. In order to avoid CREATE_TRACE_POINTS in
the header a wrapper call is used and the trace/events/sched.h include
is moved before sched.h in kernel/sched/core.
Signed-off-by: Phil Auld
CC: Qais Yousef
CC
On Mon, May 11, 2020 at 09:25:43PM +0200 Vincent Guittot wrote:
> On Thu, 7 May 2020 at 22:36, Phil Auld wrote:
> >
> > sched/fair: Fix enqueue_task_fair warning some more
> >
> > The recent patch, fe61468b2cb (sched/fair: Fix enqueue_task_fair warning)
> > did
Hi Dietmar,
On Tue, May 12, 2020 at 11:00:16AM +0200 Dietmar Eggemann wrote:
> On 11/05/2020 22:44, Phil Auld wrote:
> > On Mon, May 11, 2020 at 09:25:43PM +0200 Vincent Guittot wrote:
> >> On Thu, 7 May 2020 at 22:36, Phil Auld wrote:
> >>>
> >>> sche
add fixes and review tags.
Suggested-by: Vincent Guittot
Signed-off-by: Phil Auld
Cc: Peter Zijlstra (Intel)
Cc: Vincent Guittot
Cc: Ingo Molnar
Cc: Juri Lelli
Reviewed-by: Vincent Guittot
Reviewed-by: Dietmar Eggemann
Fixes: fe61468b2cb (sched/fair: Fix enqueue_task_fair warning)
---
ke
On Tue, May 12, 2020 at 04:10:48PM +0200 Peter Zijlstra wrote:
> On Tue, May 12, 2020 at 09:52:22AM -0400, Phil Auld wrote:
> > sched/fair: Fix enqueue_task_fair warning some more
> >
> > The recent patch, fe61468b2cb (sched/fair: Fix enqueue_task_fair warning)
> >
uct *p,
> int flags)
>
> }
>
> +enqueue_throttle:
> if (cfs_bandwidth_used()) {
> /*
> * When bandwidth control is enabled; the cfs_rq_throttled()
> --
> 2.17.1
>
Reviewed-by: Phil Auld
--
with this one as well. As expected, since
the first patch fixed the issue I was seeing and I wasn't hitting
the assert here anyway, I didn't hit the assert.
But I also didn't hit any other issues, new or old.
It makes sense to use the same logic flow here as enqueue_task_fair.
Reviewed-by: Phil Auld
Cheers,
Phil
--
On Fri, Jun 19, 2020 at 12:46:41PM -0400 Steven Rostedt wrote:
> On Fri, 19 Jun 2020 10:11:20 -0400
> Phil Auld wrote:
>
> >
> > diff --git a/include/trace/events/sched.h b/include/trace/events/sched.h
> > index ed168b0e2c53..a6d9fe5a68cf 100644
> > --- a/inclu
On Tue, Jun 09, 2020 at 07:05:38AM +0800 Tao Zhou wrote:
> Hi Phil,
>
> On Mon, Jun 08, 2020 at 10:53:04AM -0400, Phil Auld wrote:
> > On Sun, Jun 07, 2020 at 09:25:58AM +0800 Tao Zhou wrote:
> > > Hi,
> > >
> > > On Fri, May 01, 2020 at 06:
Hi Vincent,
On Thu, May 07, 2020 at 05:06:29PM +0200 Vincent Guittot wrote:
> Hi Phil,
>
> On Wed, 6 May 2020 at 20:05, Phil Auld wrote:
> >
> > Hi Vincent,
> >
> > Thanks for taking a look. More below...
> >
> > On Wed, May 06, 2020 at 06:36:45
g would
effect. At an initial glance I'm thinking it would be the imbalance_min
which is currently hardcoded to 2. But there may be something else...
Cheers,
Phil
> Thanks a lot!
> Jirka
>
> On Thu, May 7, 2020 at 5:54 PM Mel Gorman wrote:
> >
> > On Thu, May 07
Hi Vincent,
On Thu, May 07, 2020 at 05:06:29PM +0200 Vincent Guittot wrote:
> Hi Phil,
>
> On Wed, 6 May 2020 at 20:05, Phil Auld wrote:
> >
> > Hi Vincent,
> >
> > Thanks for taking a look. More below...
> >
> > On Wed, May 06, 2020 at 06:36:45
first loop.
Address this by calling leaf_add_rq_list if there are throttled parents while
doing the second for_each_sched_entity loop.
Suggested-by: Vincent Guittot
Signed-off-by: Phil Auld
Cc: Peter Zijlstra (Intel)
Cc: Vincent Guittot
Cc: Ingo Molnar
Cc: Juri Lelli
---
kernel/sched/fair.c | 7
Hi Qais,
On Mon, Jun 22, 2020 at 01:17:47PM +0100 Qais Yousef wrote:
> On 06/19/20 10:11, Phil Auld wrote:
> > Add a bare tracepoint trace_sched_update_nr_running_tp which tracks
> > ->nr_running CPU's rq. This is used to accurately trace this data and
> > provide
I haven't studied up on it in great detail, but isn't there a more
specific macro that doesn't need a permission argument at all?
Probably thinking of IIO_DEVICE_ATTR_RO / IIO_DEVICE_ATTR_WO
But they don't provide flexibility for the show / store method.
--
Regards
Phil Reid
that might take a bit longer.
btw, what do you want to do about shmobile_defconfig? Should we add
any changes needed for RZ/N1 to it? Note that only one IP block is the
same as R-Car.
Thanks
Phil
Arasan IP.
See https://patchwork.kernel.org/patch/8062871/
This has been tested on the Renesas RZ/ND-DB board with the RZ/N1 SoC.
Signed-off-by: Phil Edworthy
---
drivers/mmc/host/sdhci-of-arasan.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci
Hi Adrian,
On 27 February 2018 14:08, Adrian Hunter wrote:
> On 27/02/18 15:55, Phil Edworthy wrote:
> > Since the controller does not support the end-of-busy IRQ, don't use it.
> > Otherwise, on older SD cards you will get lots of these messages:
> > "mmc0: Got
Hi Shawn,
On 27 February 2018 14:28, Shawn Lin wrote:
> 在 2018/2/27 21:55, Phil Edworthy 写道:
> > Since the controller does not support the end-of-busy IRQ, don't use it.
> > Otherwise, on older SD cards you will get lots of these messages:
> > "mmc0: Got data inte
Hi Shawn,
On 27 February 2018 14:42, Shawn Lin wrote:
> On 2018/2/27 22:31, Phil Edworthy wrote:
> > Hi Shawn,
> >
> > On 27 February 2018 14:28, Shawn Lin wrote:
> >> 在 2018/2/27 21:55, Phil Edworthy 写道:
> >>> Since the controller does not
ic - not syncing: Attempted to kill init!
> exitcode=0x000b
> [0.502064]
> [0.511346] ---[ end Kernel panic - not syncing: Attempted to kill init!
> exitcode=0x000b
> [0.511346]
>
> so long,
>
> Hias
>
>>
>> Reading through this code, I'm left wondering why we switch the rodata
>> section to be writable here - if we're poking at kernel text, then
>> surely we shouldn't be the read-only data read-write?
>>
>> Should kernel_set_to_readonly also be a rodata-after-init variable?
This was my initial explanation:
1. Data which is marked __ro_after_init is initially writeable.
2. The ro_perms data covers kernel text, read-only data and __ro_after_init
data.
3. set_kernel_text_rw marks everything in ro_perms as writeable.
4. set_kernel_text_ro marks everything in ro_perms as read-only, including the
__ro_after_init data.
5. Using the function tracing code involves code modification, resulting in
calls to
__ftrace_modify_code and set_kernel_text_ro.
6. Therefore if function tracing is enabled before kernel_init has completed
then the __ro_after_init
data is made read-only prematurely.
Phil
On 10/08/2017 11:21, Dan Carpenter wrote:
> The original patch did not go through the normal review process...
>
> On Tue, Aug 08, 2017 at 01:05:02PM +0100, Phil Elwell wrote:
>> I'm all for fixing memory leaks, but freeing a block while it is still
>> being used is
On 10/08/2017 12:24, Dan Carpenter wrote:
> On Thu, Aug 10, 2017 at 11:52:42AM +0100, Phil Elwell wrote:
>> On 10/08/2017 11:21, Dan Carpenter wrote:
>>> The original patch did not go through the normal review process...
>>>
>>> On Tue, Aug 08, 2017 at
connections.
Simplifying the code by removing a bunch of gotos and returning errors
directly.
Signed-off-by: Phil Elwell
Fixes: 0adbfd4694c2 ("staging: bcm2835-audio: fix memory leak in
bcm2835_audio_open_connection()")
---
v2: Simplified following feedback from Dan Carpenter.
---
.../vc0
connections.
Simplifying the code by removing a bunch of gotos and returning errors
directly.
Signed-off-by: Phil Elwell
Fixes: 0adbfd4694c2 ("staging: bcm2835-audio: fix memory leak in
bcm2835_audio_open_connection()")
---
[Resend with v2 in subject]
v2: Simplified following feedback from Dan
, causing the waiting cores to execute random code.
Use the /memreserve/ Device Tree directive to mark the first page as
off-limits to the kernel.
See: https://github.com/raspberrypi/linux/issues/1989
Signed-off-by: Phil Elwell
---
arch/arm/boot/dts/bcm2710-rpi-3-b.dts | 4
arch/arm/boot/dts
applied then the other cores will sleep forever.
See: https://github.com/raspberrypi/linux/issues/1989
Signed-off-by: Phil Elwell
---
drivers/irqchip/irq-bcm2836.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
index e10597c
, causing the waiting cores to execute random code.
Use the /memreserve/ Device Tree directive to mark the first page as
off-limits to the kernel.
See: https://github.com/raspberrypi/linux/issues/1989
Signed-off-by: Phil Elwell
---
Changes in V2:
- Rebase against linux-next
- Drop downstream-only
On 09/05/2017 19:14, Marc Zyngier wrote:
On 09/05/17 19:08, Eric Anholt wrote:
Marc Zyngier writes:
On 09/05/17 17:59, Eric Anholt wrote:
Phil Elwell writes:
In order to reduce power consumption and bus traffic, it is sensible
for secondary cores to enter a low-power idle state when
On 09/05/2017 19:53, Marc Zyngier wrote:
On 09/05/17 19:52, Phil Elwell wrote:
On 09/05/2017 19:14, Marc Zyngier wrote:
On 09/05/17 19:08, Eric Anholt wrote:
Marc Zyngier writes:
On 09/05/17 17:59, Eric Anholt wrote:
Phil Elwell writes:
In order to reduce power consumption and bus
, rinfo->sda_gpio);
return 0;
};
A small modification to the i2c-core could be done in i2c_init_recovery to
allow:
rinfo->recover_bus == i2c_generic_scl_recovery
when scl_gpio is also set and fallback to using the core set / get scl / sda
calls
Which would remove the need f
On 10/05/2017 08:42, Marc Zyngier wrote:
> On 09/05/17 20:02, Phil Elwell wrote:
>> On 09/05/2017 19:53, Marc Zyngier wrote:
>>> On 09/05/17 19:52, Phil Elwell wrote:
>>>> On 09/05/2017 19:14, Marc Zyngier wrote:
>>>>> On 09/05/17 19:08, E
On 04/05/2017 18:51, Stefan Wahren wrote:
>
>> Phil Elwell hat am 4. Mai 2017 um 11:58 geschrieben:
>>
>>
>> vchiq_arm supports transfers less than one page and at arbitrary
>> alignment, using the dma-mapping API to perform its cache maintenance
>> (even
On 10/05/2017 09:55, Marc Zyngier wrote:
> On Wed, May 10 2017 at 9:27:10 am BST, Phil Elwell
> wrote:
>> On 10/05/2017 08:42, Marc Zyngier wrote:
>>> On 09/05/17 20:02, Phil Elwell wrote:
>>>> On 09/05/2017 19:53, Marc Zyngier wrote:
>>>>> On 09
On 10/05/2017 10:06, Greg Kroah-Hartman wrote:
> On Wed, May 10, 2017 at 09:42:43AM +0100, Phil Elwell wrote:
>> On 04/05/2017 18:51, Stefan Wahren wrote:
>>>
>>>> Phil Elwell hat am 4. Mai 2017 um 11:58 geschrieben:
>>>>
>>>>
>>>>
On 10/05/2017 11:09, Marc Zyngier wrote:
> On 10/05/17 10:05, Phil Elwell wrote:
>> On 10/05/2017 09:55, Marc Zyngier wrote:
>>> On Wed, May 10 2017 at 9:27:10 am BST, Phil Elwell
>>> wrote:
>>>> On 10/05/2017 08:42, Marc Zyngier wrote:
>>>>&
or the 2836")
>
> M.
>
The patch has some checkpatch warnings, but otherwise:
Reviewed-by: Phil Elwell
Tested-by: Phil Elwell
Thanks,
Phil
On 10/05/2017 16:31, Marc Zyngier wrote:
> On 10/05/17 16:07, Phil Elwell wrote:
>> On 10/05/2017 14:32, Marc Zyngier wrote:
>>> On 10/05/17 14:26, Marc Zyngier wrote:
>>>> One of the RPi-2/3 irqchip's key features is that it contains some
>>>>
G'day Andy,
Thanks for the review.
On 10/05/2017 21:13, Andy Shevchenko wrote:
On Wed, 2017-05-10 at 13:57 +0200, Tim Sander wrote:
This patch contains much input from Phil Reid and has been tested
on Intel/Altera Cyclone V SOC Hardware with Altera GPIO's for the
SCL and SDA GP
Hi Stefan,
On 30/05/2017 19:41, Stefan Wahren wrote:
> Hi Phil,
>
>> Phil Elwell hat am 30. Mai 2017 um 18:28 geschrieben:
>>
>>
>> Restrict clock sources for the PCM peripheral to the oscillator and
>> PLLD_PER because other source may have varying rates or
Hi Stefan,
On 30/05/2017 20:04, Stefan Wahren wrote:
> Hi Phil,
>
>> Phil Elwell hat am 30. Mai 2017 um 18:28 geschrieben:
>>
>>
>> Fractional clock dividers generate accurate average frequencies but
>> with jitter, particularly when the integer divisor is sm
jitter. The metric is the ideal rate minus the
worse deviation from that ideal using the nearest integer divisors.
Use this metric for parent selection for clocks requiring low jitter
(currently just PCM).
Signed-off-by: Phil Elwell
---
drivers/clk/bcm/clk-bcm2835.c | 40
-off-by: Phil Elwell
---
drivers/clk/bcm/clk-bcm2835.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 0258538..81ecd4c 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk
LK analagous to REGISTER_PER_CLK in patch 1.
* Renamed temporary variable idiv to int_div in patch 2.
Phil Elwell (2):
clk: bcm2835: Limit PCM clock to OSC and PLLD_PER
clk: bcm2835: Minimise clock jitter for PCM clock
drivers/clk/bcm/clk-bcm2835.c | 50 ++-
1 f
On 31/05/2017 16:58, Stefan Wahren wrote:
> Am 31.05.2017 um 17:27 schrieb Stephen Warren:
>> On 05/30/2017 06:23 AM, Phil Elwell wrote:
>>> Hi,
>>>
>>> I've run into a problem using the fixed-factor clock on Raspberry Pi
>>> and I'd
>
On 01/06/2017 07:39, Stephen Boyd wrote:
> On 05/31, Phil Elwell wrote:
>> On 31/05/2017 16:58, Stefan Wahren wrote:
>>> Am 31.05.2017 um 17:27 schrieb Stephen Warren:
>>>> On 05/30/2017 06:23 AM, Phil Elwell wrote:
>>>>> Hi,
>>>>>
&
On 31/05/2017 22:36, Eric Anholt wrote:
> Phil Elwell writes:
>
>> Fractional clock dividers generate accurate average frequencies but
>> with jitter, particularly when the integer divisor is small.
>>
>> Introduce a new metric of clock accuracy to penalise clo
On 31/05/2017 22:24, Eric Anholt wrote:
> Phil Elwell writes:
>
>> Restrict clock sources for the PCM peripheral to the oscillator and
>> PLLD_PER because other source may have varying rates or be switched off.
>> Prevent other sources from being selected by replacing th
and gave
it a comment in patch 1.
* Added a REGISTER_PCM_CLK analagous to REGISTER_PER_CLK in patch 1.
* Renamed temporary variable idiv to int_div in patch 2.
Phil Elwell (2):
clk: bcm2835: Limit PCM clock to OSC and PLLD_PER
clk: bcm2835: Minimise clock jitter for PCM clock
drivers/clk/bcm/clk
-off-by: Phil Elwell
Reviewed-by: Eric Anholt
---
drivers/clk/bcm/clk-bcm2835.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 0258538..81ecd4c 100644
--- a/drivers/clk/bcm/clk
jitter. The metric is the ideal rate minus the
worse deviation from that ideal using the nearest integer divisors.
Use this metric for parent selection for clocks requiring low jitter
(currently just PCM).
Signed-off-by: Phil Elwell
Reviewed-by: Eric Anholt
---
drivers/clk/bcm/clk-bcm2835.c | 34
jitter. The metric is the ideal rate minus the
worse deviation from that ideal using the nearest integer divisors.
Use this metric for parent selection for clocks requiring low jitter
(currently just PCM).
Signed-off-by: Phil Elwell
Reviewed-by: Eric Anholt
Acked-by: Stefan Wahren
---
drivers
Changes in v2:
* Extended bcm2835_pcm_per_parents to cover the pllh_aux slot, and gave
it a comment in patch 1.
* Added a REGISTER_PCM_CLK analagous to REGISTER_PER_CLK in patch 1.
* Renamed temporary variable idiv to int_div in patch 2.
* Fix comment formatting in patch 2.
Phil Elwell (2):
clk: bcm
-off-by: Phil Elwell
Reviewed-by: Eric Anholt
Acked-by: Stefan Wahren
---
drivers/clk/bcm/clk-bcm2835.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 0258538..49867d2 100644
--- a
re is no real negative impact as the spi-framework
does no longer rely on driver-provided DMA mappings but
maps the transfers transparently.
Signed-off-by: Martin Sperl
Submitted-by: Phil Elwell
---
drivers/mmc/host/mmc_spi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/driver
On 23/05/2017 08:58, Ulf Hansson wrote:
> On 22 May 2017 at 11:09, Phil Elwell wrote:
>> since:
>> commit 0589342c27944e50ebd7a54f5215002b6598b748
>> Author: Rob Herring
>> Date: Tue Oct 29 23:36:46 2013 -0500
>>
>>
On 05/06/2017 21:13, Stephen Boyd wrote:
> On 06/05, Phil Elwell wrote:
>> That sounds great, but it doesn't match my experience. Let me restate my
>> observations with a bit more detail.
>>
>> In this scenario there three devices in a dependency chain:
>>
>
arguably be forked off as a separate
irqchip driver, but the clock driver has already claimed the AUX_IRQ
register so some driver and DT surgery would still be required.
Eric Anholt thought that including it here is reasonable, but I'm
prepared to split it out if this is considered too hacky.
Phil E
Devices in the AUX block share a common interrupt line, with a register
indicating which devices have active IRQs. Expose this as a nested
interrupt controller to avoid IRQ sharing problems (easily observed if
UART1 and SPI1/2 are enabled simultaneously).
Signed-off-by: Phil Elwell
---
drivers
Now that the AUX block has a dedicated interrupt controller, declare it
in the Device Tree and update the bcm283x uart1 and spi1/spi2 nodes to
use it.
Signed-off-by: Phil Elwell
---
arch/arm/boot/dts/bcm283x.dtsi | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a
On 07/06/2017 13:07, Alexander Stein wrote:
> On Wednesday 07 June 2017 12:11:45, Phil Elwell wrote:
>> Devices in the AUX block share a common interrupt line, with a register
>> indicating which devices have active IRQs. Expose this as a nested
>> interrupt controller
AUX clock driver for a time when its DT node may only be
a single word register, but until then ioremap its region without
reserving it to permit sharing.
Phil Elwell (4):
clk: bcm2835: More flexible IO register remapping
dt: bindings: Add bindings for bcm2835-aux-intc
irqchip: Add
Devices in the BCM2835 AUX block share a common interrupt line, with a
register indicating which devices have active IRQs. Expose this as a
nested interrupt controller to avoid IRQ sharing problems (easily
observed if UART1 and SPI1/2 are enabled simultaneously).
Signed-off-by: Phil Elwell
it, along
with preparing for a point in the future where the clock node MEM
resource may be shrunk to the single word it actually needs.
Signed-off-by: Phil Elwell
---
arch/arm/boot/dts/bcm283x.dtsi | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a
handling
the case where this driver's MEM resource has been reduced to include
only the AUXENB register. Otherwise, use devm_ioremap to remap the
region without reserving it.
Signed-off-by: Phil Elwell
---
drivers/clk/bcm/clk-bcm2835-aux.c | 20
1 file changed, 16 inser
Add bindings documentation for brcm,bcm2835-aux-intc and human-readable
declarations for the BCM2835 AUX IRQs.
Signed-off-by: Phil Elwell
---
.../interrupt-controller/brcm,bcm2835-aux-intc.txt | 28 ++
.../interrupt-controller/bcm2835-aux-intc.h| 20
On 12/06/2017 15:59, Marc Zyngier wrote:> On 12/06/17 15:25, Phil Elwell wrote:
>> Devices in the BCM2835 AUX block share a common interrupt line, with a
>> register indicating which devices have active IRQs. Expose this as a
>> nested interrupt controller to avoid IRQ sha
ll be invalidated. This bug was masked until
the disabling of the cache flush in flush_dcache_page().
Honouring the requested transfer start- and end-points prevents the
corruption.
Fixes: cf9caf192988 ("staging: vc04_services: Replace dmac_map_area with
dmac_map_sg")
Signed-off-
Devices in the BCM2835 AUX block share a common interrupt line, with a
register indicating which devices have active IRQs. Expose this as a
nested interrupt controller to avoid IRQ sharing problems (easily
observed if UART1 and SPI1/2 are enabled simultaneously).
Signed-off-by: Phil Elwell
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