Hi Hanjun,
This patchset is fine to me and make my
D05 machine work again.So,
Tested-by: MaJun
Thanks
Majun
在 2017/5/12 11:55, Hanjun Guo 写道:
> From: Hanjun Guo
>
> Here are 3 bugfixes for mbigen:
>
> Patch 1 is a critical bugfix which to fix the mbigen probe failure,
> commit 216646
This patch works fine on my D05 board.
Tested-by: Majun
在 2016/11/14 5:59, Agustin Vega-Frias 写道:
> This allows probe deferral to work properly when a dependent device
> fails to get a valid IRQ because the IRQ domain was not registered
> at the time the resources were added to the platform_devi
Hi Hanjun:
This patch set works fine on my Hisilicon D05 board.
Feel free to add
Tested-by: Majun
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Hanjun Guo
>
> v4 -> v5:
> - Add mbigen support back with tested on with Agustin's patchset,
> and it's a good example of ho
Hi hanjun:
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Kefeng Wang
>
> Introduce mbigen_of_create_domain() to consolidate OF related
> code and prepare for ACPI later, no funtional change.
>
> Signed-off-by: Kefeng Wang
> Signed-off-by: Hanjun Guo
> Cc: Marc Zyngier
> Cc: Thomas Gleixner
> C
Hi hanjun:
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Kefeng Wang
>
> Module owner will be set by driver core, so drop it.
>
> Signed-off-by: Kefeng Wang
> Signed-off-by: Hanjun Guo
> Cc: Marc Zyngier
> Cc: Thomas Gleixner
> Cc: Ma Jun
> ---
> drivers/irqchip/irq-mbigen.c | 1 -
> 1 file
Hi hanjun:
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Hanjun Guo
>
> With the preparation of platform msi support and interrupt producer
> in DSDT, we can add mbigen ACPI support now.
>
> We are using _PRS methd to indicate number of irq pins instead
> of num_pins in DT to avoid _DSD usage in t
Hi:
在 2016/12/26 16:57, majun (Euler7) 写道:
> Hi Hanjun:
> This patch set works fine on my Hisilicon D05 board.
> Feel free to add
Based on the Patch 1/3, 2/3 of [PATCH V9 0/3] irqchip: qcom: Add IRQ combiner
driver
from Agustin Vega-Frias
https://lwn.net/Articles/709222/
>
在 2016/12/1 17:07, Marc Zyngier 写道:
> On 01/12/16 07:45, Majun wrote:
>> From: MaJun
>>
>> For current ITS driver, two level table (indirect route) is enabled when the
>> memory used
>> for LPI route table over the limit(64KB * 2) size. But this function impact
>> the
>> performance of LPI in
Hi Marc:
在 2016/12/2 17:35, Marc Zyngier 写道:
> On 02/12/16 09:29, majun (Euler7) wrote:
>>
>>
>> 在 2016/12/1 17:07, Marc Zyngier 写道:
>>> On 01/12/16 07:45, Majun wrote:
>>>> From: MaJun
>>>>
>>>> For current ITS driver, two
sorry, ignore this one..
在 2016/12/1 15:41, Majun 写道:
> From: MaJun
>
> The return value 0 from acpi_register_gsi() means irq mapping failed.
> So, we should process this case in else branch.
>
> Signed-off-by: MaJun
> ---
> drivers/acpi/resource.c | 2 +-
> 1 file changed, 1 insertion(+), 1
Hi hanjun:
This patch works fine on my D05 board.
Tested-by: MaJun
Best Regards
Majun
在 2017/3/28 20:21, Hanjun Guo 写道:
> With the preparation of platform msi support and interrupt producer
> in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
> domain mapping"), we can ad
Hi all:
在 2017/3/30 11:07, Hanjun Guo 写道:
> On 03/30/2017 01:32 AM, Lorenzo Pieralisi wrote:
>> On Wed, Mar 29, 2017 at 05:13:54PM +0100, Lorenzo Pieralisi wrote:
>>> On Wed, Mar 29, 2017 at 03:52:47PM +0100, Marc Zyngier wrote:
On 29/03/17 14:00, Hanjun Guo wrote:
> On 03/29/2017 08:38 P
Hi Marc:
在 2017/4/26 16:01, Marc Zyngier 写道:
> On 26/04/17 04:10, Hanjun Guo wrote:
>> Hi Majun,
>>
>> On 2017/4/25 10:16, Majun wrote:
>>> From: MaJun
>>>
>>> Don't minus reserved interrupts (64) when get the clear register
>>> offset,because
>>> the clear register space includes the space of t
Hi Lorenzo:
在 2017/3/31 0:54, Lorenzo Pieralisi 写道:
> On Thu, Mar 30, 2017 at 05:14:34PM +0100, John Garry wrote:
>>
>>>
>>> Perfect for me. Hanjun, I can cherry pick Marc's patch above, rework
>>> this patch and post the resulting branch for everyone to have a final
>>> test.
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