Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 729
drivers/perf/hisilicon/djtag.h | 39 +++
4 files changed, 770 insertions(+)
create mode
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c.c | 572 +++
drivers/perf
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 ++
.../devicetree
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..ce86c07 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6
Update Kconfig for Hip05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..2befa55 100644
--- a
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 516
2 files changed, 517 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 21
3 files ch
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 78
1 file changed, 78
On Wednesday 04 January 2017 04:26 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:03AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm
On Wednesday 04 January 2017 04:29 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:21AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by
Am 06.01.2017 um 14:54 schrieb Johannes Berg:
>
>> The bridge layer can use IGMP snooping to ensure that the multicast
>> stream is only transmitted to clients that are actually a member of
>> the group. Can the mac80211 feature do the same?
>
> No, it'll convert the packet for all clients that a
Am 09.01.2017 um 09:08 schrieb Johannes Berg:
> Does it make sense to implement the two in separate layers though?
>
> Clearly, this part needs to be implemented in the bridge layer due to
> the snooping knowledge, but the code is very similar to what mac80211
> has now.
Does the bridge always kn
From: Kyyaly M.
Sent: 30 October 2016 00:12
To: Kyyaly M.
Subject: RE: Is This Email Still Working.
Transaction offer contact me---> jonathan_symond...@outlook.com for
details.
On Tuesday 08 November 2016 12:32 PM, Tan Xiaojun wrote:
On 2016/11/7 21:26, Arnd Bergmann wrote:
On Wednesday, November 2, 2016 11:42:46 AM CET Anurup M wrote:
From: Tan Xiaojun
The Hisilicon Djtag is an independent component which connects
with some other components in the
On Tuesday 08 November 2016 05:13 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 1:08:31 PM CET Anurup M wrote:
On Tuesday 08 November 2016 12:32 PM, Tan Xiaojun wrote:
On 2016/11/7 21:26, Arnd Bergmann wrote:
On Wednesday, November 2, 2016 11:42:46 AM CET Anurup M wrote:
From
On Tuesday 08 November 2016 05:15 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 11:23:35 AM CET John Garry wrote:
On 07/11/2016 20:08, Arnd Bergmann wrote:
On Monday, November 7, 2016 2:15:10 PM CET John Garry wrote:
Hi Arnd,
The new bus type tries to model the djtag in a similar wa
On Tuesday 08 November 2016 08:38 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 7:16:30 PM CET Anurup M wrote:
If these are backwards compatible, just mark them as compatible in DT,
e.g. hip06 can use
compatible = "hisilicon,hip06-cpu-djtag-v1", "hisilicon,hip
On Tuesday 08 November 2016 08:40 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 1:49:43 PM CET John Garry wrote:
Hi Arnd,
Thanks for the reference.
I think the i2c interface doesn't fully satisfy our requirements as we
need more than just a slave bus address when accessing the slave
On Thursday 10 November 2016 03:10 AM, Arnd Bergmann wrote:
On Wednesday, November 9, 2016 9:58:38 AM CET Anurup M wrote:
I also see that the compatible strings have the version included in
them, and you can probably drop them by requiring them only in the
fallback:
compatible
On Wednesday 09 November 2016 02:36 PM, John Garry wrote:
I'd suggest requiring #address-cells=<1> and #size-cells=<0> in the
master
node, and listing the children by reg property. If the address is not
easily expressed as a single integer, use a larger #address-cells
value.
We already have
perf tool can list the event names.
ToDo:
1) The counter overflow handling is currently unsupported in this
patch series.
2) ACPI support.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
Documentation: perf: hisi: Documentation for HIP05/06/07
attribute group for showing the available CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
drivers/perf
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
3. Add nodes for hip06 DDRC to support uncore events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
arch/arm64/boot/dts
-off-by: Tan Xiaojun
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile| 1 +
drivers/soc/hisilicon/Kconfig | 12 +
drivers/soc/hisilicon/Makefile | 1 +
drivers/soc/hisilicon/djtag.c | 639
1. Add support for counting Hisilicon DDRC
statistics events in perf.
2. Support a total of 13 statistics events.
3. Events listed in /sys/devices//
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/Makefile | 2
event format is
-e "hisi_mn2/read_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 571
drivers/perf/hisilicon/hisi_uncore_mn.h |
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/pmu.txt | 127 +
1 file changed, 127 insertions
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node, DDR cntroller etc. These events are
all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
From: Tan Xiaojun
1) Add Hisilicon HiP05/06/07 CPU and ALGSUB system controller dts
bindings.
2) Add Hisilicon Djtag dts binding.
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../bindings/arm/hisilicon/hisilicon.txt | 82
1. Update Kconfig for Hip05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..da8dd97 100644
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..839abc8 100644
--- a/MAINTAINERS
+++ b
. Routines to enable/disable/add/del/start/stop hardware
event counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Makefile| 1 +
drivers/perf
series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (7):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..fca339e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..2a5435b 100644
--- a
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 731
drivers/perf/hisilicon/djtag.h | 39 +++
4 files changed, 772 insertions(+)
create mode
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 ++
.../devicetree
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 53
drivers/perf/hisilicon/hisi_uncore_pmu.c | 39 +++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 21 +
3 fil
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c.c | 556 +++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 326
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 501
2 files changed, 502 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 72
1 file changed, 72
On Monday 19 December 2016 10:01 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:19AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm
On Monday 19 December 2016 10:07 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:59AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup
Thanks for the review.
On Tuesday 21 March 2017 07:42 PM, Mark Rutland wrote:
Hi,
On Fri, Mar 10, 2017 at 01:27:39AM -0500, Anurup M wrote:
+HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is
Nit: that apostrophe shouldn't be there.
Ok. shall recheck
On Tuesday 21 March 2017 10:46 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:45AM -0500, Anurup M wrote:
Add hrtimer support which use poll method to avoid counter overflow
when overflow IRQ is not supported in hardware.
The L3 cache PMU use N-N SPI interrupt which has no support in
On Tuesday 21 March 2017 10:47 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:29:01AM -0500, Anurup M wrote:
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer
Thanks for the review.
On Tuesday 21 March 2017 10:22 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:31AM -0500, Anurup M wrote:
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
Nit: s/PMU's/PMUs/
Ok.
[...]
+struct hisi_l3c_hwcfg {
+ u32
On Tuesday 21 March 2017 10:58 PM, Mark Rutland wrote:
On Tue, Mar 21, 2017 at 02:07:42PM +, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:27:27AM -0500, Anurup M wrote:
+HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die
+is called as Super CPU cluster (SCCL
Thanks for the review.
On Tuesday 21 March 2017 09:21 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:22AM -0500, Anurup M wrote:
From: Tan Xiaojun
The Hisilicon Djtag is an independent component which connects
with some other components in the SoC by Debug Bus. This driver
can be
On Friday 24 March 2017 05:13 PM, Mark Rutland wrote:
How do we ensure that we don't take the interrupt in the middle of a
> >sequence of accesses to the HW?
>
>The L3 cache and MN PMU does not use the overflow IRQ and it does
>not occur here
>as the interrupt Mask register is by default maske
On Friday 24 March 2017 05:27 PM, Mark Rutland wrote:
+/* hip05/06 chips L3C bank identifier */
>+static u32 l3c_bankid_map_v1[MAX_BANKS] = {
>+0x02, 0x04, 0x01, 0x08,
>+};
>+
>+/* hip07 chip L3C bank identifier */
>+static u32 l3c_bankid_map_v2[MAX_BANKS] = {
>+0x01, 0x02, 0x03, 0x04,
On Friday 24 March 2017 05:06 PM, Mark Rutland wrote:
+#define SC_DJTAG_TIMEOUT_US(100 * USEC_PER_MSEC) /* 100ms */
> >How was this value chosen?
> >
> >How likely is a timeout?
>
>As explained in PATCH 7,
>
>The djtag -EBUSY in hardware is a very rare scenario, and by design
>of hardware
Please have a look at this patch series. Looking forward for any
feedback and comments.
Thanks,
Anurup
On Friday 10 March 2017 11:55 AM, Anurup M wrote:
Provide Support for Hisilicon SoC(HiP05/06/07) Hardware event counters.
The Hisilicon SoC HiP0x series has many uncore or non-CPU
From: Suniel Mahesh
Fixed the following checkpatch.pl warning:
line over 80 characters
Signed-off-by: Suniel Mahesh
---
Changes for v3:
- Split earlier patches into multiple commits for easy review
as suggested by Greg K-H
- New patch addition to the series
- Rebased on top of next-20170310
From: Suniel Mahesh
Fixed unbalanced braces around else statement
Add braces on all arms of the if-else statements to comply with
kernel coding style.
Signed-off-by: Suniel Mahesh
---
Changes for v3:
- Split earlier patches into multiple commits for easy review
as suggested by Greg K-H
- Mod
From: Suniel Mahesh
Fixed the following checkpatch.pl warning:
Possible unnecessary 'out of memory' message
Signed-off-by: Suniel Mahesh
---
Changes for v3:
- Split earlier patches into multiple commits for easy review
as suggested by Greg K-H
- Modified subject and description for better re
From: Suniel Mahesh
Fixed the following checkpatch.pl checks:
spaces preferred around that 'operator', spacing provided
Logical continuations should be on the previous line, modified accordingly
Unnecessary parentheses around variables, removed
Please use a blank line after function/struct/union/
From: Suniel Mahesh
Fixed the following checkpatch.pl checks:
Blank lines aren't necessary after an open brace '{'
and before a close brace '}', removed
No space is necessary after a cast, removed
Please don't use multiple blank lines, removed
Signed-off-by: Suniel Mahesh
---
Changes for v3:
-
From: Suniel Mahesh
This patch simplifies code by replacing explicit NULL comparison
with ! or unmark operator
Reported by checkpatch.pl for comparison to NULL could be
written '!foo' or 'foo'
Signed-off-by: Suniel Mahesh
---
Changes for v3:
- Split earlier patches into multiple commits for ea
From: Suniel Mahesh
Fixed the following checkpatch.pl warnings:
Block comments should align the * on each line
Block comments use * on subsequent lines
Signed-off-by: Suniel Mahesh
---
Changes for v3:
- Split earlier patches into multiple commits for easy review
as suggested by Greg K-H
- Mo
From: Suniel Mahesh
Split earlier patches into multiple commits for easy review as
suggested by Dan Carpenter.
Modified subject, description and in few patches both for
better readability as suggested by Greg KH.
Fixed the following issues reported by checkpatch.pl:
Block comments should align t
From: Suniel Mahesh
Replaced sizeof(struct foo) into sizeof(*ptr), found by checkpatch.pl
Signed-off-by: Suniel Mahesh
---
Changes for v3:
- Split earlier patches into multiple commits for easy review
as suggested by Greg K-H
- Modified description for better readability
- Rebased on top of
From: Suniel Mahesh
Fixed the following checkpatch.pl warning:
Possible unnecessary 'out of memory' message
If it is out of memory, function should return with an
appropriate error code. Since this function is of type void,
a return statement is used.
Signed-off-by: Suniel Mahesh
---
Changes fo
From: Suniel Mahesh
Split earlier patches into multiple commits for easy review as
suggested by Dan Carpenter.
Modified subject, description and in few patches both for
better readability as suggested by Greg KH.
Dropped two patches from the earler series, as they were not adding
significant val
From: Suniel Mahesh
Fixed the following checkpatch.pl checks:
Blank lines aren't necessary after an open brace '{'
and before a close brace '}', removed
No space is necessary after a cast, removed
Please don't use multiple blank lines, removed
Signed-off-by: Suniel Mahesh
---
Changes for v4:
-
From: Suniel Mahesh
Replaced sizeof(struct foo) into sizeof(*ptr), found by checkpatch.pl
Signed-off-by: Suniel Mahesh
---
Changes for v4:
- Dropped two patches from the series, as they were not adding significant value
suggested by Dan Carpenter.
staging: rtl8192e: Fix coding style, this
From: Suniel Mahesh
Fix unbalanced braces around else statement reported by checkpatch.pl
Signed-off-by: Suniel Mahesh
---
Changes for v2:
- new patch addition to the series
- Rebased on top of next-20170306
---
drivers/staging/rtl8192e/rtl8192e/rtl_core.c | 17 ++---
1 file chang
From: Suniel Mahesh
Fixed coding style issues and improved error handling, return -ENOMEM, if
it is out of memory instead of err message. Pointer comparisions with NUll
are replaced by logical NOT. Fixed unbalanced braces around else statement
and preferred to pass a pointer as an argument to s
From: Suniel Mahesh
Fix coding style issues and comments in rtl_core.c
Signed-off-by: Suniel Mahesh
---
Changes for v2:
- Split larger patch into multiple commits as suggested by Dan Carpenter
- This patch fixes coding style issues, comments in rtl_core.c reported by
checkpatch.pl
- Modified
From: Suniel Mahesh
Return -ENOMEM, if it is out of memory
Signed-off-by: Suniel Mahesh
---
Changes for v2:
- Improve error handling reported by checkpatch.pl in rtl_core.c
- new patch addition to the series
- Rebased on top of next-20170306
---
drivers/staging/rtl8192e/rtl8192e/rtl_core.c |
From: Suniel Mahesh
Prefer vzalloc(sizeof(*priv->pFirmware)...) over
vzalloc(sizeof(struct rt_firmware)...) as reported by checkpatch.pl
Signed-off-by: Suniel Mahesh
---
Changes for v2:
- new patch addition to the series
- Rebased on top of next-20170306
---
drivers/staging/rtl8192e/rtl8192e/
From: Suniel Mahesh
Pointer comparison with NULL replaced by logical NOT
Signed-off-by: Suniel Mahesh
---
Changes for v2:
- Rectify pointer comparisions reported by checkpatch.pl in rtl_core.c
- new patch addition to the series
- Rebased on top of next-20170306
---
drivers/staging/rtl8192e/rt
counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d7b7a7..c2f9806 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5958,6
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 76
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 1e95d6a..f0aa818 100644
--- a
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: Dikshit N
---
drivers/perf/hisilicon
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 773
drivers/perf/hisilicon/djtag.h | 42 +++
4 files changed, 817 insertions(+)
create mode
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 489
2 files changed, 490 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch/arm64/boot/dts/hisilicon
interval of 10 seconds is used for the hrtimer.
Signed-off-by: Dikshit N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 47 ++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 82
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17
On Friday 03 March 2017 12:20 PM, Rob Herring wrote:
On Thu, Mar 02, 2017 at 05:48:36AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
On 11/4/2016 10:06 PM, Salil Mehta wrote:
> From: Lijun Ou
>
> In old code, It only added the interface for querying non-specific
> QP. This patch mainly adds an interface for querying QP1.
>
> Signed-off-by: Lijun Ou
> Reviewed-by: Wei Hu (Xavier)
> Signed-off-by: Salil Mehta
> ---
> dri
On 11/4/2016 10:06 PM, Salil Mehta wrote:
> From: Shaobo Xu
>
> IB core has implemented the calculation of GIDs and the management
> of GID tables, and it is now responsible to supply query function
> for GIDs. So the calculation of GIDs and the management of GID
> tables in the RoCE driver is
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
On Friday 24 February 2017 08:34 AM, Anurup M wrote:
+static int hisi_mn_init_irqs_fdt(struct device *dev,
+struct hisi_pmu *mn_pmu)
+{
+struct hisi_mn_data *mn_data = mn_pmu->hwmod_data;
+struct hisi_djtag_client *client = mn_data->client;
+int irq = -1, nu
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..5b988f5 100644
--- a
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 771
drivers/perf/hisilicon/djtag.h | 40 +++
4 files changed, 813 insertions(+)
create mode
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