在 2017-08-17 11:40，Chen-Yu Tsai 写道：
The BPI-M3 is an Allwinner A83T based SBC in the Bananapi/Bpi family.
It is roughly the same form factor as the BPI-M1+, with roughly the
same peripherals and connectors:
- 2GB LPDDR3 DRAM
- 8GB eMMC
- Micro-SD card slot
- HDMI output
- Headset (ster
在 2017-10-05 14:58，Kalle Valo 写道：
Icenowy Zheng writes:
于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
写到:
On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>
>
> 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo
写到:
&g
在 2017-10-16 17:32，Maxime Ripard 写道：
On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote:
>> + interrupts = ;
>> + clocks = <&ccu CLK_BUS_OHCI1>,
>> + <&ccu CLK_BUS_EHCI1>,
&g
在 2017-10-16 17:11，Maxime Ripard 写道：
On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be
claimed.
Why?
Allwinner didn't document this, but if the SRAM is not claimed, the
DE2 MMIO zone is totally not acces
在 2017-10-16 16:00，Maxime Ripard 写道：
Hi,
I've applied all the other patches.
On Sat, Oct 14, 2017 at 12:02:50PM +0800, Chen-Yu Tsai wrote:
The display backend, as well as other peripherals that have a DRAM
clock gate and access DRAM directly, bypassing the system bus,
address the DRAM starting
在 2017-10-17 17:06，Maxime Ripard 写道：
The current code has the wrong macro to get the registers offsets of
the
UI-registers, with an off-by-0x1000 error.
It works so far by accident, since the UI channel used everywhere else
is
the number of VI planes, which has always been 1 so far, and the o
在 2017-10-17 17:06，Maxime Ripard 写道：
Add support for the A83T display pipeline.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
drivers/gpu/drm/sun4i/sun4i_drv.c | 2 ++
drivers/gpu/drm/sun4i/sun4i_tcon.c
在 2017-05-26 03:26，Jagan Teki 写道：
From: Jagan Teki
Orangepi Prime is an open-source single-board computer
using the Allwinner h5 SOC.
Sorry but I have already added this board and it's
scheduled at 4.13.
H5 Orangepi Prime has
- Quad-core Cortex-A53
- 2GB DDR3
- Debug TTL UART
- 1000M/100M
在 2017-05-27 00:44，Jagan Teki 写道：
On Fri, May 26, 2017 at 10:10 PM, wrote:
在 2017-05-26 03:26，Jagan Teki 写道：
From: Jagan Teki
Orangepi Prime is an open-source single-board computer
using the Allwinner h5 SOC.
Sorry but I have already added this board and it's
scheduled at 4.13.
Ohh, u
在 2017-04-16 14:51，Icenowy Zheng 写道：
A new usbid of UTV007 is found in a newly bought device.
The usbid is 1f71:3301.
The ID on the chip is:
UTV007
A89029.1
1520L18K1
Both video and audio is tested with the modified usbtv driver.
Signed-off-by: Icenowy Zheng
Acked-by: Lubomir Rintel
Ping
在 2017-05-29 16:59，Maxime Ripard 写道：
On Thu, May 25, 2017 at 10:28:24PM +0800, Icenowy Zheng wrote:
>>>> + compatible = "allwinner,sun8i-v3s-de2-mixer";
>>>> + reg = <0x0110 0x10>;
>>>
>>
在 2017-05-29 21:11，Chen-Yu Tsai 写道：
On Sat, May 27, 2017 at 06:23:04PM +0800, Icenowy Zheng wrote:
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng
在 2017-05-31 01:42，Jagan Teki 写道：
From: Jagan Teki
NanoPi M1 Plus is designed and developed by FriendlyElec
using the Allwinner 64-bit H5 SOC.
Copy'n'paste error?
NanoPi Neo2 key features
- Allwinner H5, Quad-core 64-bit Cortex-A53
- 512MB DDR3 RAM
- microSD slot
- 10/100/1000M Ethernet
-
在 2017-09-11 23:55，Icenowy Zheng 写道：
This patchset adds devicetree-side support of SimpleFB on Allwinner H3
SoC.
The DE2 CCU is initialized and used by the SimpleFB node, in order to
furtherly coexist with the DRM code.
The first patch adds pipelines for DE2 displays in simplefb-sunxi
device
在 2017-10-16 20:06，Maxime Ripard 写道：
On Mon, Oct 16, 2017 at 05:39:58PM +0800, icen...@aosc.io wrote:
在 2017-10-16 17:32，Maxime Ripard 写道：
> On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote:
> > >> +interrupts = ;
> > >> +
在 2017-10-19 14:48，Chen-Yu Tsai 写道：
On Wed, Oct 18, 2017 at 11:00 PM, Joonas Kylmälä
wrote:
Hi,
Chen-Yu Tsai:
mmc1 only has 1 possible pinmux setting.
What if someone is using the MMC with bus width 1 and then using the
remaining 3 pins for something else?
I would very much like to see su
在 2017-09-11 23:55，Icenowy Zheng 写道：
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch
在 2017-10-16 20:09，Maxime Ripard 写道：
On Mon, Oct 16, 2017 at 05:41:10PM +0800, icen...@aosc.io wrote:
在 2017-10-16 17:11，Maxime Ripard 写道：
> On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> > A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be
> &
在 2017-10-27 23:06，Icenowy Zheng 写道：
This patchset adds support for the SimpleFB on Allwinner SoCs with
"Display Engine 2.0".
PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs.
PATCH 4 adds the pipeline strings for DE2 SimpleFB.
PATCH 5 to 7 adds necessary device tree nodes (D
在 2017-03-27 21:47，Maxime Ripard 写道：
On Mon, Mar 27, 2017 at 05:11:29PM +0800, Icenowy Zheng wrote:
2017年3月26日 21:10于 Maxime Ripard 写道：
>
> On Thu, Mar 23, 2017 at 07:17:03AM +0800, Icenowy Zheng wrote:
> >
> >
> > 23.03.2017, 04:09, "Maxime Ripard" :
> &
在 2017-04-17 04:57，Maxime Ripard 写道：
On Tue, Apr 11, 2017 at 09:28:55PM +0800, icen...@aosc.io wrote:
在 2017-04-11 17:13，Maxime Ripard 写道：
> On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
> > The CPU on Allwinner H3 can do dynamic frequency scaling.
> >
>
在 2017-04-19 13:09，Chen-Yu Tsai 写道：
As part of our effort to move pinctrl/GPIO interlocking into the
driver where it belongs, this patch drops the definition and usage
of the mmc0_cd_pin_reference_design pinmux setting for the default
mmc0 card detect GPIO pin.
Signed-off-by: Chen-Yu Tsai
---
在 2017-04-20 13:58，Maxime Ripard 写道：
On Tue, Apr 18, 2017 at 06:56:43PM +0800, Icenowy Zheng wrote:
于 2017年4月18日 GMT+08:00 下午3:00:16, Maxime Ripard
写到:
>On Mon, Apr 17, 2017 at 07:57:37PM +0800, Icenowy Zheng wrote:
>> Allwinner A64 SoC features a NMI controller, which i
于 2017年4月20日 GMT+08:00 下午4:37:07, Maxime Ripard
写到:
On Tue, Apr 18, 2017 at 06:47:56PM +0800, Icenowy Zheng wrote:
>> + /* Get the physical address of the buffer in memory */
>> + gem = drm_fb_cma_get_gem_obj(fb, 0);
>> +
>> + DRM_DEBUG_DRIVER("Usi
在 2017-04-27 21:28，Maxime Ripard 写道：
On Wed, Apr 26, 2017 at 11:20:14PM +0800, Icenowy Zheng wrote:
Allwinner A64 have a RSB controller like the one on A23/A33 SoCs.
Add it and its pinmux.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v2:
- Removed bonus properties in
在 2017-04-05 10:27，Chen-Yu Tsai 写道：
On Wed, Apr 5, 2017 at 3:53 AM, Icenowy Zheng wrote:
在 2017年04月05日 03:28, Sean Paul 写道:
On Thu, Mar 30, 2017 at 03:46:06AM +0800, Icenowy Zheng wrote:
As we are going to add support for the Allwinner DE2 Mixer in
sun4i-drm
driver, we will finally
在 2017-04-11 17:13，Maxime Ripard 写道：
On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
The CPU on Allwinner H3 can do dynamic frequency scaling.
Add a DVFS table based on the one tweaked by Armbian developers, which
are proven to work stably on BSP kernels.
Frequencies higher
在 2017-04-24 15:17，Maxime Ripard 写道：
On Thu, Apr 20, 2017 at 03:03:38PM +0800, icen...@aosc.io wrote:
在 2017-04-20 13:58，Maxime Ripard 写道：
> On Tue, Apr 18, 2017 at 06:56:43PM +0800, Icenowy Zheng wrote:
> >
> >
> > 于 2017年4月18日 GMT+08:00 下午3:00:16, Maxime Ripard
> &g
在 2017-04-24 16:51，Maxime Ripard 写道：
Hi,
On Sun, Apr 23, 2017 at 06:37:45PM +0800, Icenowy Zheng wrote:
+static const struct of_device_id sunxi_de2_clk_ids[] = {
+ {
+ .compatible = "allwinner,sun8i-a83t-de2-clk",
+ .data = &sun8i_a83
在 2017-04-25 00:00，Icenowy Zheng 写道：
Add support for the newly imported compatible for the A64 R_INTC in
irq-sunxi-nmi driver
Signed-off-by: Icenowy Zheng
---
New patch in v4, which is part of NMI refactor.
drivers/irqchip/irq-sunxi-nmi.c | 13 +
1 file changed, 13 insertions
在 2017-04-25 10:17，Chen-Yu Tsai 写道：
On Tue, Apr 25, 2017 at 12:01 AM, Icenowy Zheng
wrote:
As axp20x-regulator now supports AXP803, add a cell for it.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v4:
- Added a trailing comma for new cell, for easier further cell
在 2017-06-27 23:18，Ziping Chen 写道：
2017-06-27 1:15 GMT+08:00 Maxime Ripard
:
Hi,
On Sat, Jun 24, 2017 at 10:45:14AM +0800, Ziping Chen wrote:
From: Ziping Chen
Allwinner A83T SoC has a low res adc like the one
in Allwinner A10 SoC.
Add binding for it.
Signed-off-by: Ziping Chen
Acked-by:
在 2017-05-19 15:19，Maxime Ripard 写道：
On Fri, May 19, 2017 at 11:03:33AM +0800, Icenowy Zheng wrote:
>The patch looks OK, but given the module is removable, I think it
>should be
>an overlay. The overlay would enable WiFi + Bluetooth, and all the
>peripherals needed to connect them.
在 2017-06-30 00:23，David Miller 写道：
From: Corentin Labbe
Date: Tue, 27 Jun 2017 11:28:01 +0200
The current way to find if the phy is internal is to compare DT
phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the
在 2017-07-07 04:46，Maxime Ripard 写道：
Hi,
On Thu, Jul 06, 2017 at 10:28:21PM +0800, Icenowy Zheng wrote:
The PH16 pin has a function with mux id 0x5, which is the DET pin of
the
"sim" (smart card reader) IP block.
This function is missing both in the old A10 and A20 drivers, so it&#
在 2017-07-20 06:59，Ondřej Jirman 写道：
Hi,
Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800:
From: Icenowy Zheng
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
The mux 3 of R_CCU is still the internal
在 2017-07-20 10:03，icen...@aosc.io 写道：
在 2017-07-20 06:59，Ondřej Jirman 写道：
Hi,
Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800:
From: Icenowy Zheng
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
The
在 2017-07-20 10:03，icen...@aosc.io 写道：
在 2017-07-20 06:59，Ondřej Jirman 写道：
Hi,
Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800:
From: Icenowy Zheng
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
The
在 2017-07-20 06:59，Ondřej Jirman 写道：
Hi,
Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800:
From: Icenowy Zheng
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
The mux 3 of R_CCU is still the internal
在 2017-07-21 15:49，Chen-Yu Tsai 写道：
On Fri, Jul 21, 2017 at 3:44 PM, Icenowy Zheng wrote:
于 2017年7月21日 GMT+08:00 下午3:42:07, Chen-Yu Tsai 写到:
On Fri, Jul 21, 2017 at 7:07 AM, Icenowy Zheng
wrote:
Banana Pi M64 board uses an AXP803 PMIC.
Enable the PMIC and its regulators.
As we have now
在 2017-05-29 15:34，Chen-Yu Tsai 写道：
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Chang
在 2017-09-14 23:51，Levin, Alexander (Sasha Levin) 写道：
From: Icenowy Zheng
[ Upstream commit bb021cda2ccf45ee9470bf0f8c55323ad1c761ae ]
As DVFS for A33 doesn't exist in 4.9, this patch doesn't affect 4.9
at all.
The CPUX clock on A33, which is for the Cortex-A7 cores, is desi
在 2017-08-23 15:43，Laurent Pinchart 写道：
Hi Hans,
On Wednesday, 23 August 2017 09:52:00 EEST Hans Verkuil wrote:
On 08/22/2017 10:17 PM, Maxime Ripard wrote:
> On Tue, Aug 22, 2017 at 08:43:35AM +0200, Hans Verkuil wrote:
> +static int sun6i_video_link_setup(struct media_entity *entity,
在 2017-08-23 04:05，Maxime Ripard 写道：
Hi,
On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
From: Chen-Yu Tsai
The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple
在 2017-08-23 22:35，Maxime Ripard 写道：
On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > + reg = <0x01c0f000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> > + clock-names = "ahb", "mmc";
> > +
在 2017-08-24 14:07，Maxime Ripard 写道：
On Wed, Aug 23, 2017 at 11:13:04PM +0800, icen...@aosc.io wrote:
在 2017-08-23 22:35，Maxime Ripard 写道：
> On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > > + reg = <0x01c0f000 0x1000>;
> > > > + clocks
在 2017-08-22 21:39，Andrew Lunn 写道：
On Tue, Aug 22, 2017 at 12:03:59PM +0800, Icenowy Zheng wrote:
From: Icenowy Zheng
Some RTL8211E chips have broken GbE function, which needs a hack to
fix. It's said that this fix will affect the performance on not-buggy
PHYs, so it should only be enabl
在 2017-09-16 17:45，Quentin Schulz 写道：
Hi Icenowy,
On 14/09/2017 16:52, Icenowy Zheng wrote:
This adds support for the Allwinner H3 thermal sensor.
Allwinner H3 has a thermal sensor like the one in A33, but have its
registers nearly all re-arranged, sample clock moved to CCU and a pair
of bus
在 2017-09-18 16:30，Maxime Ripard 写道：
On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:
于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard
写到:
>On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a thermal sensor like the one in A33, but
在 2017-09-19 19:55，Maxime Ripard 写道：
On Tue, Sep 19, 2017 at 04:23:14PM +0800, Icenowy Zheng wrote:
于 2017年9月19日 GMT+08:00 下午4:20:19, Maxime Ripard
写到:
>On Mon, Sep 18, 2017 at 11:42:04PM +0800, Icenowy Zheng wrote:
>> Allwinner A64/H5 SoCs come with a SID controller like the
在 2017-09-02 00:30，Philipp Rossak 写道：
From: Philipp Rossak
The WiFi side of the AP6212 WiFi/BT combo module is connected to
mmc1. There are also GPIOs for enable and interrupts.
Enable WiFi on this board by enabling mmc1 and adding the power
sequencing clocks and GPIO, as well as the chip's in
在 2017-08-22 13:23，Icenowy Zheng 写道：
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng
Maxime, Chen-Yu, ping.
Could you queue this patchs
在 2017-08-19 17:11，Chen-Yu Tsai 写道：
On Tue, Aug 15, 2017 at 4:52 PM, wrote:
在 2017-08-15 13:55，Icenowy Zheng 写道：
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy
在 2017-08-20 08:59，kbuild test robot 写道：
Hi Chen-Yu,
[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.13-rc5 next-20170817]
[if your patch is applied to the wrong git tree, please drop us a note
to help improve the system]
In fact this tree shouldn't be applied on robh's t
在 2017-08-21 16:40，Maxime Ripard 写道：
On Thu, Aug 17, 2017 at 03:49:26PM +0800, Icenowy Zheng wrote:
Q8 tablets with Allwinner A33 SoC now come with two kind of LCD,
either
800x480 or 1024x600.
In order for sun4i-drm to be able to choose correct LCD configuration,
two different device trees
在 2017-08-21 17:34，Maxime Ripard 写道：
Hi,
On Sun, Aug 20, 2017 at 01:29:57PM +0800, Icenowy Zheng wrote:
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/arm/sunxi/README | 6
在 2017-05-11 03:23，Maxime Ripard 写道：
Hi,
On Thu, May 04, 2017 at 04:05:18PM +0800, Chen-Yu Tsai wrote:
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The A10s Olinuxino has an HDMI connector. Make sure we can use it.
>
> Acked-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
>
在 2017-06-01 02:43，Maxime Ripard 写道：
On Wed, May 24, 2017 at 04:25:46PM +0800, Icenowy Zheng wrote:
于 2017年5月24日 GMT+08:00 下午3:30:19, Maxime Ripard
写到:
>On Tue, May 23, 2017 at 09:00:59PM +0800, icen...@aosc.io wrote:
>> 在 2017-05-23 20:53，Maxime Ripard 写道：
>> > On Mon,
在 2017-05-15 17:24，Maxime Ripard 写道：
On Mon, May 15, 2017 at 12:30:43AM +0800, Icenowy Zheng wrote:
+ de2_clocks: clock@100 {
display_clocks would be better there, we don't have to dissociate de1
with de2
How about de_clocks ? (See A80
在 2017-05-17 17:27，icen...@aosc.io 写道：
在 2017-05-15 17:24，Maxime Ripard 写道：
On Mon, May 15, 2017 at 12:30:43AM +0800, Icenowy Zheng wrote:
+ de2_clocks: clock@100 {
display_clocks would be better there, we don't have to dissociate de1
with de2
How about de_clocks ?
7 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
> >> 于 2017年5月20日 GMT+08:00 上午2:03:30, Maxime Ripard >
> > electrons.com> 写到:
> >> >On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng wrote:
> >> >> Allwinner H3 features a TV encoder similar
在 2017-06-05 00:01，Icenowy Zheng 写道：
Allwinner H3 SoC features a TV Encoder like the one in Allwinner A13,
which can only output TV Composite signal.
The display pipeline of H3 is also special -- it has two mixers and
two TCONs, of which the connection can be swapped. The TCONs do not
have
在 2017-06-09 22:46，Maxime Ripard 写道：
On Thu, Jun 08, 2017 at 01:01:53PM +0800, icen...@aosc.io wrote:
在 2017-06-07 22:38，Maxime Ripard 写道：
> On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > >I have no idea what this is supposed to be doing either.
> > >
在 2017-06-10 22:57，icen...@aosc.io 写道：
在 2017-06-09 22:46，Maxime Ripard 写道：
On Thu, Jun 08, 2017 at 01:01:53PM +0800, icen...@aosc.io wrote:
在 2017-06-07 22:38，Maxime Ripard 写道：
> On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > >I have no idea what this is su
在 2017-06-10 05:24，Jernej Škrabec 写道：
Hi!
Dne petek, 09. junij 2017 ob 18:51:02 CEST je Icenowy Zheng napisal(a):
于 2017年6月10日 GMT+08:00 上午12:49:15, Maxime Ripard
electrons.com> 写到:
>On Wed, Jun 07, 2017 at 04:48:50PM +0800, Icenowy Zheng wrote:
>> >> @@ -189,6 +
在 2017-06-07 17:38，Maxime Ripard 写道：
On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng wrote:
Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
but has a internal fixed clock divider that divides the TCON1 clock
(called TVE clock in datasheet) by 11.
Add support for
在 2017-06-07 17:42，Maxime Ripard 写道：
On Mon, Jun 05, 2017 at 12:01:48AM +0800, Icenowy Zheng wrote:
+ soc {
+ display_clocks: clock@100 {
+ compatible = "allwinner,sun8i-a83t-de2-clk";
+ reg = <0x0100
在 2017-05-04 21:05，Maxime Ripard 写道：
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic processing and feed data to TCON, like the
old
backends and frontends.
Add suppo
在 2017-05-04 21:05，Maxime Ripard 写道：
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic processing and feed data to TCON, like the
old
backends and frontends.
Add suppo
在 2017-05-05 00:50，icen...@aosc.io 写道：
在 2017-05-04 21:05，Maxime Ripard 写道：
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic processing and feed data to TCON, lik
在 2017-05-05 00:57，icen...@aosc.io 写道：
在 2017-05-05 00:50，icen...@aosc.io 写道：
在 2017-05-04 21:05，Maxime Ripard 写道：
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic proc
在 2017-05-03 19:59，Maxime Ripard 写道：
It appears that the total vertical resolution needs to be doubled when
we're not in interlaced. Make sure that is the case.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff -
在 2017-05-05 10:56，Chen-Yu Tsai 写道：
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
As we are going to add support for the Allwinner DE2 engine in
sun4i-drm
driver, we will finally have two types of display engines -- the DE1
backend and the DE2 mixer. They both do some display blending
在 2017-05-05 11:31，Chen-Yu Tsai 写道：
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
which have RGB LCD output.
Please also mention that it only has one mixer.
For the subject, you could just say "Add d
在 2017-05-06 04:04，Maxime Ripard 写道：
Hi,
On Fri, May 05, 2017 at 06:31:57PM +0800, Yong Deng wrote:
V3S's usb otg device reset bit should be 24, not 23.
Signed-off-by: Yong Deng
Reviewed-By: Icenowy Zheng
Applied, thanks.
Maxime
Maybe it should also apply to 4.11 stable?
Cc
在 2017-09-25 18:27，Maxime Ripard 写道：
On Mon, Sep 25, 2017 at 10:12:09AM +, Icenowy Zheng wrote:
于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
写到:
>Hi,
>
>On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
>> This patchset imports simple DVFS support for Al
在 2017-09-28 18:27，Maxime Ripard 写道：
Hi,
On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote:
The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.
Add the mux and pll notifiers for A64 CPU
在 2017-09-28 22:20，Maxime Ripard 写道：
On Thu, Sep 28, 2017 at 10:42:39AM +, icen...@aosc.io wrote:
> On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:
> > The A64 PLL_CPU clock has the same instability if some factor changed
> > without the PLL gated like other
在 2017-08-22 13:23，Icenowy Zheng 写道：
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng
Maxime,
Ping. Have you checked this patchset?
---
Doc
在 2017-10-05 14:58，Kalle Valo 写道：
Icenowy Zheng writes:
于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
写到:
On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>
>
> 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo
写到:
&g
在 2017-06-07 22:38，Maxime Ripard 写道：
On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
>I have no idea what this is supposed to be doing either.
>
>I might be wrong, but I really feel like there's a big mismatch
>between your commit log, and what you actually impl
在 2017-05-24 16:14，Maxime Ripard 写道：
On Sat, May 20, 2017 at 02:00:22AM +0800, Icenowy Zheng wrote:
于 2017年5月20日 GMT+08:00 上午1:57:53, Maxime Ripard
写到:
>On Thu, May 18, 2017 at 12:43:46AM +0800, Icenowy Zheng wrote:
>> Some SoC's DE2 has two mixers. Defaultly the mixer0 i
hen-Yu Tsai napisal(a):
> > > On Sat, May 20, 2017 at 2:23 AM, Jernej Škrabec
> > wrote:
> > > > Hi,
> > > >
> > > > Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
> > > >> 于 2017年5月20日 GMT+08:00 上午2:03:30, Maxim
在 2017-08-04 10:23，Chen-Yu Tsai 写道：
On Tue, Aug 1, 2017 at 10:54 PM, Icenowy Zheng wrote:
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when
was not worked a
在 2017-08-06 10:39，Chen-Yu Tsai 写道：
On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote:
The configuration struct of A64 EMMC(MMC2) compatible used to
have the needs_new_timings variable missing, which lead to NULL
pointer dereference now when trying to set up the old timings mode, as
在 2017-07-24 11:07，Chen-Yu Tsai 写道：
On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng wrote:
From: Ondrej Jirman
H3/H5 SoCs contain an I2C controller optionally available
on the PL0 and PL1 pins. This patch adds pinmux configuration
for this controller.
Signed-off-by: Ondrej Jirman
[Icenowy
在 2017-07-24 11:03，Chen-Yu Tsai 写道：
On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng wrote:
From: Ondrej Jirman
SY8106A is an I2C attached single output regulator made by Silergy
Corp,
which is used on several Allwinner H3/H5 SBCs to control the power
supply of the ARM cores.
Add a driver
在 2017-07-24 11:33，Chen-Yu Tsai 写道：
On Mon, Jul 24, 2017 at 11:18 AM, wrote:
在 2017-07-24 11:03，Chen-Yu Tsai 写道：
On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng
wrote:
From: Ondrej Jirman
SY8106A is an I2C attached single output regulator made by Silergy
Corp,
which is used on
在 2017-07-24 14:02，Chen-Yu Tsai 写道：
On Sun, Jul 23, 2017 at 10:13 PM, Icenowy Zheng
wrote:
As the H3 SoC, which is also in sun8i line, has totally different
register map for the thermal sensor (a cut down version of GPADC), we
should rename A23/A33-specified registers to contain A23, in order
在 2017-07-24 15:58，Maxime Ripard 写道：
On Sat, Jul 22, 2017 at 10:28:49AM +0800, Icenowy Zheng wrote:
Allwinner A64 SoC has an EMAC which is used to provide Ethernet
function on several boards.
The EMAC itself doesn't have a fixed MAC address, but the sunxi
mainline U-Boot have the abili
在 2017-07-25 16:29，Chen-Yu Tsai 写道：
default ARCH_SUNXI
On Tue, Jul 25, 2017 at 3:47 PM, Maxime Ripard
wrote:
Hi Chen-Yu,
On Tue, Jul 25, 2017 at 01:09:16PM +0800, Chen-Yu Tsai wrote:
The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and
1 cluster of 4 Cortex-A15s.
This patch adds su
在 2017-07-22 10:50，Icenowy Zheng 写道：
This patchset contains only two patches.
The first one is a minor fix for the A10 pinctrl driver, add a function
of a pin, which used to be missing in A10/A20 pinctrl driver. Thanks
for
Chen-Yu for discovering it when reviewing my R40 pinctrl patchset
在 2017-08-07 21:09，Linus Walleij 写道：
On Tue, Aug 1, 2017 at 4:54 PM, Icenowy Zheng wrote:
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when
developing the driver, which makes IRQ not working.
Fix the IRQ
在 2017-08-12 01:42，Jagan Teki 写道：
On Fri, Aug 11, 2017 at 6:01 PM, Jagan Teki
wrote:
From: Jagan Teki
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.
Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to
在 2017-07-17 16:52，Maxime Ripard 写道：
On Fri, Jul 14, 2017 at 05:49:23PM +0300, Priit Laes wrote:
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes
---
drivers/clk/sunxi-ng/ccu_div.c | 15 +--
drivers/clk/sunxi-ng/ccu_div
在 2017-05-29 15:34，Chen-Yu Tsai 写道：
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Chang
在 2017-08-12 12:13，Chen-Yu Tsai 写道：
On Sat, Aug 12, 2017 at 11:07 AM, wrote:
在 2017-07-17 16:52，Maxime Ripard 写道：
On Fri, Jul 14, 2017 at 05:49:23PM +0300, Priit Laes wrote:
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes
---
在 2017-08-12 12:04，Chen-Yu Tsai 写道：
On Sat, Jul 22, 2017 at 11:00 AM, wrote:
在 2017-05-29 15:34，Chen-Yu Tsai 写道：
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
[...]
+
+/*
+ * For the special bit in gate part, please see the BSP source code
at
+ *
https
在 2017-08-12 20:43，Icenowy Zheng 写道：
From: Priit Laes
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes
Oh sorry, it misses my SoB.
---
It's based on the patch in v6 of the A10/A20 CCU patchset, but with
ccu_div_round
在 2017-08-12 20:43，Icenowy Zheng 写道：
From: Priit Laes
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes
Signed-off-by: Icenowy Zheng
---
It's based on the patch in v6 of the A10/A20 CCU patchset, but with
ccu_div_round
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