On Thu, May 24, 2018 at 5:35 AM Vijay Viswanath
wrote:
> On 5/22/2018 11:40 PM, Evan Green wrote:
> > On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath > wrote:
> >
> >> In addition to offsets of certain registers changing, the registers in
> >> core_mem hav
On Thu, May 24, 2018 at 6:01 AM Vijay Viswanath
wrote:
> On 5/22/2018 11:42 PM, Evan Green wrote:
> > Hi Vijay. Thanks for this patch.
> >
> > On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath > wrote:
> >
> >> From: Sayali Lokhande
> >
...
> &
Hi Georgi,
On Fri, Mar 9, 2018 at 1:11 PM Georgi Djakov
wrote:
> Add driver for the Qualcomm interconnect buses found in msm8916 based
> platforms.
> Signed-off-by: Georgi Djakov
> ---
>drivers/interconnect/Kconfig| 5 +
>drivers/interconnect/Makefile | 1 +
>driver
On Fri, Mar 9, 2018 at 1:10 PM Georgi Djakov
wrote:
> Currently we support only platform data for specifying the interconnect
> endpoints. As now the endpoints are hard-coded into the consumer driver
> this may leed to complications when a single driver is used by multiple
Nit: s/leed/lead/
-Ev
On Fri, Mar 9, 2018 at 1:11 PM Georgi Djakov
wrote:
> On some Qualcomm SoCs, there is a remote processor, which controls some of
> the Network-On-Chip interconnect resources. Other CPUs express their needs
> by communicating with this processor. Add a driver to handle comminication
> with this re
Hi Georgi,
On Fri, Mar 9, 2018 at 1:12 PM Georgi Djakov
wrote:
> This patch introduce a new API to get requirements and configure the
> interconnect buses across the entire chipset to fit with the current
> demand.
> The API is using a consumer/provider-based model, where the providers are
> th
Green
---
drivers/pinctrl/qcom/pinctrl-msm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
b/drivers/pinctrl/qcom/pinctrl-msm.c
index 0e22f52b2a19..d48a74ddbc1f 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom
oot/dts/qcom/pm8998.dtsi | 55
> 2 files changed, 88 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pm8005.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/pm8998.dtsi
>
Reviewed-by: Evan Green
On Wed, May 16, 2018 at 2:52 AM Adrian Hunter
wrote:
> On 02/05/18 02:47, Evan Green wrote:
> > For a controller with SDHCI_QUIRK_NO_CARD_NO_RESET, there are several
> > conditions where sdhci_do_reset is called under a spinlock with
interrupts
> > disabled. The card d
+++
> include/linux/soc/qcom/llcc-qcom.h | 180
> 5 files changed, 642 insertions(+)
> create mode 100644 drivers/soc/qcom/llcc-sdm845.c
> create mode 100644 drivers/soc/qcom/llcc-slice.c
> create mode 100644 include/linux/soc/qcom/llcc-qcom.h
Thanks Rishabh.
Reviewed-by: Evan Green
On Wed, Dec 12, 2018 at 10:41 AM Jonathan Cameron
wrote:
>
> On Sat, 8 Dec 2018 12:05:15 +
> Jonathan Cameron wrote:
>
> > On Tue, 4 Dec 2018 11:57:32 -0800
> > Matthias Kaehlcke wrote:
> >
> > > On Tue, Dec 04, 2018 at 11:14:19AM -0800, Evan Green
with these changes I can run as a different user, and drop
all other privileges.
Evan Green (2):
soc: qcom: rmtfs-mem: Add class to enable uevents
soc: qcom: rmtfs-mem: Make sysfs attributes world-readable
drivers/soc/qcom/rmtfs_mem.c | 29 +
1 file change
Currently the qcom_rmtfs_memN devices are entirely invisible to the udev world.
Add a class to the rmtfs device so that uevents fire when the device is added.
Signed-off-by: Evan Green
---
drivers/soc/qcom/rmtfs_mem.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions
those attributes readable by all.
Signed-off-by: Evan Green
---
drivers/soc/qcom/rmtfs_mem.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c
index 0bf800ee2a978..4eeb9f02e7889 100644
--- a/drivers/soc/qcom/rmtfs_
On Mon, Dec 10, 2018 at 9:31 AM Evan Green wrote:
>
> On Wed, Dec 5, 2018 at 7:15 PM Martin K. Petersen
> wrote:
> >
> >
> > Evan,
> >
> > > Ah, I see. But I think it's useful to reflect max_discard_sectors,
> > > max_write_zeroes_sector
d serial characters, rather than edited ones.
Either way, this looks good to me.
Reviewed-by: Evan Green
o in order to proceed. This
probably could never happen, especially with locks around consoles and
uart ports that act as barriers.
Reviewed-by: Evan Green
On Fri, Dec 7, 2018 at 7:52 PM Kishon Vijay Abraham I wrote:
>
> Hi,
>
> On 07/12/18 2:16 PM, Vivek Gautam wrote:
> > On Fri, Dec 7, 2018 at 5:06 AM Evan Green wrote:
> >>
> >> Utilize the newly fixed up DT bindings to get the tx2 and rx2 register
> >
On Wed, Dec 5, 2018 at 7:15 PM Martin K. Petersen
wrote:
>
>
> Evan,
>
> > Ah, I see. But I think it's useful to reflect max_discard_sectors,
> > max_write_zeroes_sectors, discard_granularity, and discard_alignment
> > from the block device to the loop device. With the exception of
> > discard_ali
med ufsphy to phy (Vivek)
- Removed #clock-cells (Vivek)
Can Guo (1):
arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
Evan Green (4):
dt-bindings: phy-qcom-qmp: Fix register underspecification
phy: qcom-qmp: Utilize fully-specified DT registers
arm64: dts: qcom: sdm845: add UFS
that don't
provide a pipe clock. Also, document the pcs_misc register region, which
was being quietly supplied and used.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Fix incorrect register val
don't exist, which
reverts to the original behavior of overreaching and prints a complaint.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
As Doug mentioned, this should land before the dts patches land, otherwise
the old driver code will use the tx2 register region as pcs_misc.
Add the second lane registers for the USB PHY, now that the
QMP phy bindings have been updated. This way the driver can stop
reaching beyond its register region to get at the second lane.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
Reviewed-by: Bjorn Andersson
---
Changes in v7
From: Can Guo
Enable the UFS host controller and PHY on sdm845-mtp.
Signed-off-by: Can Guo
Signed-off-by: Evan Green
Reviewed-by: Vivek Gautam
Reviewed-by: Douglas Anderson
---
Changes in v7: None
Changes in v6:
- Fix renamed nodes in MTP (Bjorn)
Changes in v5: None
Changes in v4: None
Add the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green
Signed-off-by: Douglas Anderson
Reviewed-by: Bjorn Andersson
---
As Doug mentioned in v2, this should land after (or with) the driver fix
in this series.
Changes in v7: None
Changes in v6:
- Removed resets and reset-names
to Vivek for testing msm8996.
This patch sits atop the UFS device nodes series [1].
[1] https://lore.kernel.org/lkml/20181210192826.241350-1-evgr...@chromium.org/
Changes in v2:
- Rebased onto phy/next
Evan Green (4):
dt-bindings: phy-qcom-qmp: Move #clock-cells to child
arm64: dts: qcom:
Move #clock-cells into the child node and set it to 0 to conform to the
proper binding specification.
Signed-off-by: Evan Green
Reviewed-by: Stephen Boyd
Tested-by: Vivek Gautam
---
Changes in v2: None
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 --
1 file changed, 4 insertions(+), 2
Register a simple clock provider for the PHY pipe clock sources so that
device tree users can point at these clocks via phandles to the lane
nodes.
Signed-off-by: Evan Green
Reviewed-by: Stephen Boyd
Tested-by: Vivek Gautam
---
Changes in v2:
- Rebased onto phy/next
drivers/phy/qualcomm
cell.
Fix these incomplete and broken bindings. Move the #clock-cells into the
child node, since that is the actual clock provider, and not all
instances of qcom-qmp-phy are clock providers. Also set #clock-cells to
zero, since there's nothing to pass to it.
Signed-off-by: Evan Green
Review
Move #clock-cells into the child node for instances of the qcom-qmp-phy
nodes, and set it to zero, in accordance with the proper bindings. PHYs
that don't provide clocks don't have #clock-cells, and so are left alone.
Signed-off-by: Evan Green
Reviewed-by: Stephen Boyd
---
Changes i
*pctrl = dev_get_drvdata(dev);
>
> return pinctrl_force_sleep(pctrl->pctrl);
> }
>
> -static int msm_pinctrl_resume(struct device *dev)
> +static __maybe_unused int msm_pinctrl_resume(struct device *dev)
> {
> struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
>
Thanks Arnd.
Reviewed-by: Evan Green
On Thu, Dec 20, 2018 at 5:19 PM Brian Norris wrote:
>
> Hi Evan,
>
> On Mon, Dec 17, 2018 at 04:08:33PM -0800, Evan Green wrote:
> > Currently the qcom_rmtfs_memN devices are entirely invisible to the udev
> > world.
> > Add a class to the rmtfs device so that u
with these changes I can run as a different user, and drop
all other privileges.
Changes in v2:
- Moved class registration/deregistration into init/exit routines (Brian)
Evan Green (2):
soc: qcom: rmtfs-mem: Add class to enable uevents
soc: qcom: rmtfs-mem: Make sysfs attributes world-rea
those attributes readable by all.
Signed-off-by: Evan Green
Reviewed-by: Brian Norris
---
Changes in v2: None
drivers/soc/qcom/rmtfs_mem.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c
index 99a1363e
Currently the qcom_rmtfs_memN devices are entirely invisible to the udev world.
Add a class to the rmtfs device so that uevents fire when the device is added.
Signed-off-by: Evan Green
---
Changes in v2:
- Moved class registration/deregistration into init/exit routines (Brian)
drivers/soc
ritel_relaxed(M_CMD_ABORT_EN, uport->membase +
> + writel(M_CMD_ABORT_EN, uport->membase +
> SE_GENI_M_IRQ_CLEAR);
Here too.
> }
> - writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
> + writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
> }
>
> static void qcom_geni_serial_start_rx(struct uart_port *uport)
> @@ -637,26 +622,20 @@ static void qcom_geni_serial_start_rx(struct uart_port
> *uport)
> u32 status;
> struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
>
> - status = readl_relaxed(uport->membase + SE_GENI_STATUS);
> + status = readl(uport->membase + SE_GENI_STATUS);
> if (status & S_GENI_CMD_ACTIVE)
> qcom_geni_serial_stop_rx(uport);
>
> - /*
> -* Ensure setup command write is not re-ordered before checking
> -* the status of the Secondary Sequencer.
> -*/
> - mb();
> -
mmm, good deletes.
With the minor line coalescing fixed you can add my:
Reviewed-by: Evan Green
of the name was never really correct,
since this is also used by the regular uart_ops as well. You could
optionally fold in a rename of this define in this change.
I was also trying to reason about why that - 2 was there, and if that
should be - UART_CONSOLE_RX_WM. But I don't really get why it's there,
so I can't say for sure that it's conceptually the same value. So I
guess that's fine as is.
Reviewed-by: Evan Green
gt; irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
> irq_en &= ~M_CMD_DONE_EN;
> - if (port->xfer_mode == GENI_SE_FIFO) {
> - irq_en &= ~M_TX_FIFO_WATERMARK_EN;
> - writel(0, uport->membase +
> -SE_GENI_TX_WATERMARK_REG);
> - }
> + irq_en &= ~M_TX_FIFO_WATERMARK_EN;
This could be further coalesced into irq_en &= ~(M_CMD_DONE_EN |
M_TX_FIFO_WATERMARK_EN);
Reviewed-by: Evan Green
; 2.20.1.415.g653613c723-goog
>
I did a brief search tour of unsigned in this file, and also found
rxstale in qcom_geni_serial_port_setup. Other than that and the commit
message:
Reviewed-by: Evan Green
the rpmh_request structure and
> cause KASAN to complain.
>
> Let's fix this by allocating a chunk of completions for each message and
> waiting for all of them to be completed before returning from the batch
> API. Alternatively, we could wait for the last message in the batch, but
On Fri, Dec 21, 2018 at 2:05 PM Bjorn Andersson
wrote:
>
> On Fri 21 Dec 12:10 PST 2018, Evan Green wrote:
>
> > Currently the qcom_rmtfs_memN devices are entirely invisible to the udev
> > world.
> > Add a class to the rmtfs device so that uevents fire wh
with these changes I can run as a different user, and drop
all other privileges.
Changes in v3:
- Removed spurious whitespace changes (Brian, Bjorn)
Changes in v2:
- Moved class registration/deregistration into init/exit routines (Brian)
Evan Green (2):
soc: qcom: rmtfs-mem: Add class to e
Currently the qcom_rmtfs_memN devices are entirely invisible to the udev world.
Add a class to the rmtfs device so that uevents fire when the device is added.
Signed-off-by: Evan Green
Reviewed-by: Brian Norris
Reviewed-by: Bjorn Andersson
---
Changes in v3:
- Removed spurious whitespace
those attributes readable by all.
Signed-off-by: Evan Green
Reviewed-by: Brian Norris
Reviewed-by: Bjorn Andersson
---
Changes in v3: None
Changes in v2: None
drivers/soc/qcom/rmtfs_mem.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rmtfs_mem.c b/dr
On Mon, Oct 8, 2018 at 6:22 AM Veerabhadrarao Badiganti
wrote:
>
> From: Vijay Viswanath
>
> Some controllers can have internal mechanism to inform the SW that it
> is ready for voltage switching. For such controllers, changing voltage
> before the HW is ready can result in various issues.
>
> Du
On Mon, Oct 8, 2018 at 6:26 AM Veerabhadrarao Badiganti
wrote:
>
> On few SDHCI-MSM controllers, the host controller's clock tuning
> circuit may go out of sync if controller clocks are gated which
> eventually will result in data CRC, command CRC/timeout errors.
> To overcome this h/w limitation,
.
Can Guo (1):
arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
Evan Green (1):
arm64: dts: qcom: sdm845: add UFS controller
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 11 +
arch/arm64/boot/dts/qcom/sdm845.dtsi| 66 +
2 files changed, 77 insertions
This change adds the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 66
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64
From: Can Guo
This change enables the UFS host controller and PHY on sdm845-mtp.
Signed-off-by: Can Guo
Signed-off-by: Evan Green
---
I was unable to test this on an MTP, if somebody could give this a try I would
be grateful. This applies atop agross/for-next, since it needs the regulators
the "-names" description but I found myself
> confused.
>
> * As per the code not all "pcie qmp phys" have resets. Specifically
> note that the "has_lane_rst" property in the driver is false for
> "ipq8074-qmp-pcie-phy". Thus make it clear exactly which PHYs need
> child nodes with resets.
>
> Signed-off-by: Douglas Anderson
Reviewed-by: Evan Green
57 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
Reviewed-by: Evan Green
64/boot/dts/qcom/sdm845.dtsi | 62
>
> 1 file changed, 62 insertions(+)
>
Reviewed-by: Evan Green
On Mon, Oct 22, 2018 at 5:29 PM Rob Herring wrote:
>
> On Thu, Oct 18, 2018 at 02:09:29PM -0700, Evan Green wrote:
> > This change adds register regions for the second lane of dual-lane nodes.
> > This additional specification is needed so that the driver can stop
> > re
orum, hosted by The Linux Foundation.
>
I think this makes sense to me, though the paths through here can be a
little winding.
Reviewed-by: Evan Green
):
arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
Evan Green (4):
dt-bindings: phy-qcom-qmp: Fix register underspecification
phy: qcom-qmp: Utilize fully-specified DT registers
arm64: dts: qcom: sdm845: add UFS controller
arm64: dts: qcom: sdm845: Add USB PHY lane two
.../devicetre
don't exist, which
reverts to the original behavior of overreaching and prints a complaint.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
As Doug mentioned, this should land before the dts patches land, otherwise
the old driver code will use the tx2 register region as pcs_misc.
that don't
provide a pipe clock. Also, document the pcs_misc register region, which
was being quietly supplied and used.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Changes in v4:
- Remove "status" from DT binding example (Rob)
Chan
Add the second lane registers for the USB PHY, now that the
QMP phy bindings have been updated. This way the driver can stop
reaching beyond its register region to get at the second lane.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
Changes in v4: None
Changes in v3:
- Removed
Add the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green
Signed-off-by: Douglas Anderson
---
As Doug mentioned in v2, this should land after (or with) the driver fix
in this series.
Changes in v4: None
Changes in v3: None
Changes in v2:
- Renamed ufsphy to phy (Vivek)
- Removed
From: Can Guo
Enable the UFS host controller and PHY on sdm845-mtp.
Signed-off-by: Can Guo
Signed-off-by: Evan Green
Reviewed-by: Vivek Gautam
Reviewed-by: Douglas Anderson
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 14
On Mon, Oct 8, 2018 at 7:09 PM Raju P.L.S.S.S.N wrote:
>
> From: Lina Iyer
>
> Controllers may be in 'solver' state, where they could be in autonomous
> mode executing low power modes for their hardware and as such are not
> available for sending active votes. Device driver may notify RPMH API
>
On Thu, Oct 25, 2018 at 1:38 PM Doug Anderson wrote:
>
> Hi,
> On Thu, Oct 25, 2018 at 10:23 AM Manu Gautam wrote:
> >
> > Correct address for pcs_misc register region of USB3 QMP UNI PHY.
> > These registers are used during runtime-suspend/resume routines
> > of phy.
> >
> > Fixes: ca4db2b538a1
that don't
provide a pipe clock. Also, document the pcs_misc register region, which
was being quietly supplied and used.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Changes in v5:
- Fix incorrect register value in example, copied from real life!
Ch
Add the second lane registers for the USB PHY, now that the
QMP phy bindings have been updated. This way the driver can stop
reaching beyond its register region to get at the second lane.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
Changes in v5: None
Changes in v4: None
Add the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green
Signed-off-by: Douglas Anderson
---
As Doug mentioned in v2, this should land after (or with) the driver fix
in this series.
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Renamed ufsphy to phy
arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
Evan Green (4):
dt-bindings: phy-qcom-qmp: Fix register underspecification
phy: qcom-qmp: Utilize fully-specified DT registers
arm64: dts: qcom: sdm845: add UFS controller
arm64: dts: qcom: sdm845: Add USB PHY lane two
.../devicetree/bi
don't exist, which
reverts to the original behavior of overreaching and prints a complaint.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
As Doug mentioned, this should land before the dts patches land, otherwise
the old driver code will use the tx2 register region as pcs_misc.
From: Can Guo
Enable the UFS host controller and PHY on sdm845-mtp.
Signed-off-by: Can Guo
Signed-off-by: Evan Green
Reviewed-by: Vivek Gautam
Reviewed-by: Douglas Anderson
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/qcom
On Thu, Oct 18, 2018 at 4:33 AM Vivek Gautam
wrote:
>
> Hi Evan,
>
> On Wed, Oct 17, 2018 at 10:55 PM Evan Green wrote:
> >
> > This change adds the UFS controller and PHY to SDM845.
> >
> > Signed-off-by: Evan Green
> > Signed-off-by: Douglas Ander
optional for PHYs that don't
provide a pipe clock. Also, document the pcs_misc register region, which
was being quietly supplied and used.
Signed-off-by: Evan Green
---
This applies atop linux-next 20181018 with the addition of Doug's
changes [1] and [2].
[1] https://lore.kerne
This change adds the second lane registers for the USB PHY, now that the
QMP phy bindings have been updated. This way the driver can stop
reaching beyond its register region to get at the second lane.
Signed-off-by: Evan Green
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++--
1 file
From: Can Guo
This change enables the UFS host controller and PHY on sdm845-mtp.
Signed-off-by: Can Guo
Signed-off-by: Evan Green
Reviewed-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts
This change adds the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 67
1 file changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64
ister regions don't exist, which
reverts to the original behavior of overreaching and prints a complaint.
Signed-off-by: Evan Green
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 51 +++--
1 file changed, 38 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/qu
/lkml/20181012213926.253765-1-diand...@chromium.org/
Can Guo (1):
arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
Evan Green (4):
dt-bindings: phy-qcom-qmp: Fix register underspecification
phy: qcom-qmp: Utilize fully-specified DT registers
arm64: dts: qcom: sdm845: add UFS controller
arm64
This change removes a parent map and parent name array that
appear to be completely unreferenced.
Signed-off-by: Evan Green
---
drivers/clk/qcom/gcc-sdm845.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index
On Thu, Oct 18, 2018 at 3:29 PM Stephen Boyd wrote:
>
> Quoting Evan Green (2018-10-18 15:03:50)
> > This change removes a parent map and parent name array that
> > appear to be completely unreferenced.
> >
> > Signed-off-by: Evan Green
> > ---
>
> Appli
On Thu, Sep 20, 2018 at 11:29 AM Georgi Djakov wrote:
>
> The interconnect API provides an interface for consumer drivers to express
> their bandwidth needs in the SoC. This data is aggregated and the on-chip
> interconnect hardware is configured to the appropriate power/performance
> profile.
>
>
file changed, 62 insertions(+)
>
Reviewed-by: Evan Green
that don't
provide a pipe clock. Also, document the pcs_misc register region, which
was being quietly supplied and used.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
Changes in v3: None
Changes in v2:
- Added dt bindings change, corresponding driver fixup, and USB PHY
erroneous fixup for USB UniPro PHY, which is not dual lane (Doug)
Changes in v2:
- Added dt bindings change, corresponding driver fixup, and USB PHY fixup
- Renamed ufsphy to phy (Vivek)
- Removed #clock-cells (Vivek)
Can Guo (1):
arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
Evan Green (4
don't exist, which
reverts to the original behavior of overreaching and prints a complaint.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
---
As Doug mentioned, this should land before the dts patches land, otherwise
the old driver code will use the tx2 register region as pcs_misc.
Add the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green
Signed-off-by: Douglas Anderson
---
As Doug mentioned in v2, this should land after (or with) the driver fix
in this series.
Changes in v3: None
Changes in v2:
- Renamed ufsphy to phy (Vivek)
- Removed #clock-cells (Vivek
From: Can Guo
Enable the UFS host controller and PHY on sdm845-mtp.
Signed-off-by: Can Guo
Signed-off-by: Evan Green
Reviewed-by: Vivek Gautam
Reviewed-by: Douglas Anderson
---
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 14 ++
1 file
Add the second lane registers for the USB PHY, now that the
QMP phy bindings have been updated. This way the driver can stop
reaching beyond its register region to get at the second lane.
Signed-off-by: Evan Green
---
Changes in v3:
- Removed erroneous fixup for USB UniPro PHY, which is not
Hi Taniya,
On Thu, Jul 12, 2018 at 11:06 AM Taniya Das wrote:
>
> The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
> for changing the frequency of CPUs. The driver implements the cpufreq
> driver interface for this hardware engine.
>
> Signed-off-by: Saravana Kannan
> Sig
Hi Vijay,
On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath
wrote:
> From: Sayali Lokhande
> For SDCC version 5.0.0, MCI registers are removed from SDCC
> interface and some registers are moved to HC.
> Define a new data structure where we can statically define
> the address offsets for the regis
On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath
wrote:
> In addition to offsets of certain registers changing, the registers in
> core_mem have been shifted to HC mem as well. To access these registers,
> define msm version specific functions. These functions can be loaded
> into the function poi
Hi Vijay. Thanks for this patch.
On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath
wrote:
> From: Sayali Lokhande
> For SDCC version 5.0.0 and higher, new compatible string
> "qcom,sdhci-msm-v5" is added.
> Based on the msm variant, pick the relevant variant data and
> use it for register read/
Hi Taniya,
On Mon, Apr 2, 2018 at 3:33 AM Taniya Das wrote:
> Hello Evan,
> Thanks for the review comments.
> On 3/30/2018 3:19 AM, Evan Green wrote:
> > Hi Taniya,
> >
> > On Wed, Mar 28, 2018 at 11:19 PM Taniya Das wrote:
> >
> >
-qcom-qusb2.c | 39
+++
> 1 file changed, 39 insertions(+)
Reviewed-by: Evan Green
quot;phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom
chips")
> Reviewed-by: Vivek Gautam
> Cc: stable # 4.14+
> Signed-off-by: Manu Gautam
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
> 1 file changed, 4 insertions(+)
Reviewed-by: Evan Green
Hi Rishabh,
On Tue, Mar 27, 2018 at 11:54 AM Rishabh Bhatnagar
wrote:
> LLCC (Last Level Cache Controller) provides additional cache memory
> in the system. LLCC is partitioned into muliple slices and each
> slice getting its own priority, size, ID and other config parameters.
> LLCC driver prog
Hi Manu,
On Thu, Mar 29, 2018 at 4:06 AM Manu Gautam wrote:
> QMP PHY for USB/PCIE requires pipe_clk for locking of
> retime buffers at the pipe interface. Driver checks for
> PHY_STATUS without enabling pipe_clk due to which
> phy_init() fails with initialization timeout.
> Though pipe_clk is o
On Wed, Apr 25, 2018 at 9:54 PM Stephen Rothwell
wrote:
> Hi Evan,
> On Thu, 26 Apr 2018 03:39:25 + Evan Green
wrote:
> >
> > Guenter and I had a fix for compile test here, which had failures that
> > looked similar:
> >
> > https://lkml.org/lkml/2018/
Hi Rishabh,
On Mon, Apr 23, 2018 at 4:11 PM Rishabh Bhatnagar
wrote:
> LLCC (Last Level Cache Controller) provides additional cache memory
> in the system. LLCC is partitioned into multiple slices and each
> slice gets its own priority, size, ID and other config parameters.
> LLCC driver program
For a controller with SDHCI_QUIRK_NO_CARD_NO_RESET, there are several
conditions where sdhci_do_reset is called under a spinlock with interrupts
disabled. The card detect is often a GPIO, which might sleep. Avoid
asking for the card detect status if interrupts are disabled to prevent
a warning like
This change removes the read-only clauses from the documentation
for UFS attributes, which are now writable.
Signed-off-by: Evan Green
---
Documentation/ABI/testing/sysfs-driver-ufs | 17 +
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/Documentation/ABI/testing
On Wed, Jun 6, 2018 at 11:09 AM Georgi Djakov wrote:
>
> Hi Evan,
>
> On 06/06/2018 05:59 PM, Georgi Djakov wrote:
> >>> +
> >>> +/**
> >>> + * icc_node_create() - create a node
> >>> + * @id: node id
> >>> + *
> >>> + * Return: icc_node pointer on success, or ERR_PTR() on error
> >>> + */
> >>> +
On Wed, Apr 25, 2018 at 3:42 PM Stephen Rothwell
wrote:
> Hi Andy,
> After merging the qcom tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
> ERROR: "geni_se_select_mode" [drivers/tty/serial/qcom_geni_serial.ko]
undefined!
> ERROR: "geni_se_init" [drivers/tty/serial/qco
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