Introduce SMP support for MIPS Creator CI20, which is
based on Ingenic JZ4780 SoC.
Add "CONFIG_SMP=y" and "CONFIG_NR_CPUS=2" to support SMP.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
No change.
v2->v3:
No change.
v3->v4:
Rebase on top of kernel 5.6
Add 'cpus' node to the jz4740.dtsi, jz4770.dtsi, jz4780.dtsi
and x1000.dtsi files.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
No change.
v2->v3:
No change.
v3->v4:
Rebase on to
Enable clock event handling on per CPU core basis.
Make sure that interrupts raised on the first core execute
event handlers on the correct CPU core.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
1.Adjust function naming
Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Change the two Document from txt to yaml.
v2-
Introduce SMP support for MIPS Creator CI20, which is
based on Ingenic JZ4780 SoC.
周琰杰 (Zhou Yanjie) (6):
MIPS: JZ4780: Introduce SMP support.
MIPS: CI20: Modify DTS to support high resolution timer for SMP.
clocksource: Ingenic: Add high resolution timer support for SMP.
dt-bindings
Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for
per core local timer, #2 for clocksource.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
No change.
v2->v3:
No change.
v3->v4:
LK_SSIMUX" when initializing the clocks.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, and gates of CPU, PCLK
are also added.
3.Use "CLK_OF_DECLARE_DRIVER" like the other CGU drivers.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v5:
New patch.
V5->
Add support for the clocks provided by the CGU in the Ingenic X1830
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
1.Use two fields (pll_reg & bypass_reg) instead of the 2-values
array
v8->v9:
Add Paul Cercueil's Reviewed-by, somehow his emails are not displayed
on the mailing list and patchwork of clock framework subsystem.
v8->v9:
Add Paul Cercueil's Reviewed-by, somehow his emails are not displayed
on the mailing list and patchwork of clock framework subsystem.
周琰杰 (Zhou Yanjie) (6):
clk: Ingenic: Remove unnecessary spinlock when reading registers.
clk: Ingenic: Adjust cgu code to make it compatible wi
multiplier,
so a new "rate_multiplier" was introduced. And adjust the
code in jz47xx-cgu.c and x1000-cgu.c, make it to be
compatible with the new cgu code.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v2->v3:
Adjust order from [1/5] in v2 to [2/5]
00_CLK_SSIMUX", otherwise an error will occurs when
initializing the clock. These ABIs are only used for X1000, and
I'm sure that no other devicetree out there is using these ABIs,
so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST are also added.
Signed-
It is not necessary to use spinlock when reading registers,
so remove it from cgu.c.
Suggested-by: Paul Cercueil
Suggested-by: Paul Burton
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2->v3:
Adjust order from [5/5] in v2 to [
Add the clock bindings for the X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Rob Herring
---
Notes:
v1->v2:
Change my Signed-off-by from "Zhou Yanjie "
to "周琰杰 (Zhou Yanjie) " because
the old mailbox is in an unstable state.
Hi
在 2020/8/27 下午9:50, Paul Cercueil 写道:
Le jeu. 27 août 2020 à 16:25, Felipe Balbi a écrit :
Hi,
Paul Cercueil writes:
@@ -172,7 +172,8 @@ static int ingenic_usb_phy_init(struct usb_phy
*phy)
return err;
}
- priv->soc_info->usb_phy_init(phy);
+ reg = priv
wing issue:
[FAILED] Failed to start Raise network interfaces.
Fix this problem by select CONFIG_JZ4780_EFUSE by default in the
ci20_defconfig.
Fixes: 19c968222934 ("MIPS: DTS: CI20: make DM9000 Ethernet
controller use NVMEM to find the default MAC address").
Signed-off-by: 周琰杰 (Zhou Yan
周琰杰 (Zhou Yanjie) (1):
MIPS: CI20: Update defconfig for EFUSE.
arch/mips/configs/ci20_defconfig | 1 +
1 file changed, 1 insertion(+)
--
2.11.0
e651 ("USB: PHY: JZ4770: Add support for new
Ingenic SoCs.").
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/usb/phy/phy-jz4770.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/phy/phy-jz4770.c b/drivers/usb/phy/phy-jz4770.c
index d4ee3cb721ea..f6d3731581eb 100644
--- a
Fix the warning that appears during Static analysis.
周琰杰 (Zhou Yanjie) (1):
USB: PHY: JZ4770: Fix static checker warning.
drivers/usb/phy/phy-jz4770.c | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
--
2.11.0
Hi Paul,
在 2020/9/4 下午10:10, Paul Cercueil 写道:
Hi Zhou,
Le lun. 31 août 2020 à 21:50, 周琰杰 (Zhou Yanjie)
a écrit :
Used the generic PHY framework API to create the PHY,
and move the driver to driver/phy/ingenic.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by
Hi Paul,
在 2020/9/6 下午10:17, Paul Cercueil 写道:
Hi Zhou,
Le ven. 4 sept. 2020 à 15:27, Paul Cercueil a
écrit :
Hi Zhou,
Le lun. 31 août 2020 à 23:43, 周琰杰 (Zhou Yanjie)
a écrit :
Add SSI pins support for the JZ4770 SoC and the
JZ4780 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie
Hi Paul,
在 2020/9/6 下午10:26, Paul Cercueil 写道:
Hi Zhou,
Le lun. 31 août 2020 à 23:43, 周琰杰 (Zhou Yanjie)
a écrit :
Correct the pullup and pulldown parameters of JZ4780 to make them
consistent with the parameters on the datasheet.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New
Hi Paul,
在 2020/9/7 上午1:15, Paul Cercueil 写道:
Le lun. 7 sept. 2020 à 1:06, Zhou Yanjie a
écrit :
Hi Paul,
在 2020/9/4 下午10:10, Paul Cercueil 写道:
Hi Zhou,
Le lun. 31 août 2020 à 21:50, 周琰杰 (Zhou Yanjie)
a écrit :
Used the generic PHY framework API to create the PHY,
and move the
Used the generic PHY framework API to create the PHY,
and move the driver to driver/phy/ingenic.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/phy/Kconfig| 1
Used the generic PHY framework API to create the PHY,
and move the driver to driver/phy/ingenic.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/phy/Kconfig| 1
v1->v2:
Fix bug, ".of_match_table = of_match_ptr(ingenic_usb_phy_of_matches)" is wrong
and should be replaced with ".of_match_table = ingenic_usb_phy_of_matches".
周琰杰 (Zhou Yanjie) (1):
USB: PHY: JZ4770: Use the generic PHY framework.
drivers/phy/Kconfig
Used the generic PHY framework API to create the PHY,
and move the driver to driver/phy/ingenic.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Fix bug, ".of_match_table = of_m
1.Add SSI pins support for JZ4770 and JZ4780.
2.Correct the pullup and pulldown parameters of JZ4780.
3.Add I2S pins support for JZ4780, X1000, X1500, and X1830.
周琰杰 (Zhou Yanjie) (3):
pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780.
pinctrl: Ingenic: Correct the pullup and
Correct the pullup and pulldown parameters of JZ4780 to make them
consistent with the parameters on the datasheet.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff
Add SSI pins support for the JZ4770 SoC and the
JZ4780 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Rebase on top of kernel 5.9-rc3.
drivers/pinctrl/pinctrl-ingenic.c | 267 ++
1 file changed, 267 insertions(+)
diff --gi
1.Add I2S pins support for the JZ4780 SoC.
2.Add I2S pins support for the X1000 SoC.
3.Add I2S pins support for the X1500 SoC.
4.Add I2S pins support for the X1830 SoC.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 70
Hi Rob,
在 2020/10/13 下午9:29, Rob Herring 写道:
On Thu, Oct 08, 2020 at 02:14:07AM +0800, 周琰杰 (Zhou Yanjie) wrote:
The new OST has one global timer and two or four percpu timers, so there will
be three
combinations in the upcoming new OST driver: the original GLOBAL_TIMER +
PERCPU_TIMER,
the
Hello Maciej & Paul,
在 2020/8/22 上午10:29, Maciej W. Rozycki 写道:
Hi Paul,
FAOD is not a hack, but an optimisation measure
so that features known to be hardwired for a given machine/CPU do not have
to be dynamically queried every time referred. In some cases that results
in large portions of c
Hi Rob,
在 2020/10/26 下午9:13, Rob Herring 写道:
On Sat, Oct 17, 2020 at 12:56:02AM +0800, 周琰杰 (Zhou Yanjie) wrote:
The new OST has one global timer and two or four percpu timers, so there
will be three combinations in the upcoming new OST driver: the original
GLOBAL_TIMER + PERCPU_TIMER, the new
cause
errors in the existing codes when registering and configuring the clocks.
Currently, in the mainline, only X1000 and X1830 are using sysost driver,
and the upcoming X2000 will also use sysost driver. This patch has been
tested on all three SoCs and all works fine.
Tested-by: 周正 (Zhou Zheng)
Sign
to the commit message.
周琰杰 (Zhou Yanjie) (1):
dt-bindings: timer: Add new OST support for the upcoming new driver.
include/dt-bindings/clock/ingenic,sysost.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
--
2.11.0
在 2020/8/19 下午11:35, Paul Cercueil 写道:
Hi Zhou,
Le mer. 19 août 2020 à 22:12, Zhou Yanjie
a écrit :
Hi Paul,
I have some good news and some bad news.
Good news is:
I tested this series of patches on CU1000-Neo & CU1830-Neo, and it
can boot normally and log in to debian normally.
xisting related drivers and
the SoCs whitch using these drivers, so we should be able to exchange
them safely.
v1->v2:
Rewrite the commit message so that each line is less than 80 characters.
周琰杰 (Zhou Yanjie) (1):
dt-bindings: timer: Add new OST support for the upcoming new driver.
include
-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Rewrite the commit message so that each line is less than 80 characters.
include/dt-bindings/clock/ingenic,sysost.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/include/dt-bindi
Move Ingenic USB PHY bindings from Documentation/devicetree/bindings/usb
to Documentation/devicetree/bindings/phy, and add bindings for JZ4775 SoC
and X2000 SoC.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v8:
New patch.
v8->v9:
Correct the path errors in "ing
Remove unnecessary "of_match_ptr()", because Ingenic SoCs all
depend on Device Tree.
Suggested-by: Paul Cercueil
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v3:
New patch.
v3->v4:
No change.
v4->v5:
Add Paul Cercue
1.Refresh defconfig of CI20 to support OTG and RNG.
2.Refresh defconfig of CU1000-Neo to support OTG/RNG/OST/SC16IS752.
3.Refresh defconfig of CU1830-Neo to support OTG/DTRNG/OST/SC16IS752.
Tested-by: 周正 (Zhou Zheng)
Tested by: H. Nikolaus Schaller # CI20/jz4780
Signed-off-by: 周琰杰 (Zhou Yanjie
v1->v2:
1.Add the otg_power node for otg_phy's vcc_supply.
2.Move assigned-clocks in the otg node into the cgu node.
3.Move the position of the SSI node.
4.Select CONFIG_JZ4780_EFUSE as default.
周琰杰 (Zhou Yanjie) (2):
MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
MIPS:
. Nikolaus Schaller # CI20/jz4780
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
1.Add the otg_power node for otg_phy's vcc_supply.
2.Move assigned-clocks in the otg node into the cgu node.
3.Move the position of the SSI node.
arch/mips/boot/dts/ingenic/ci20.dts
ary "platform_set_drvdata".
3.Remove the "dev" field in priv structure, and use &phy->dev instead.
v7->v8:
Add support for Ingenic JZ4775 SoC and X2000 SoC.
v8->v9:
Correct the path errors in "ingenic,phy-usb.yaml" and "ingenic,cgu.yaml".
周琰杰 (
)
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Fix bug, ".of_match_table = of_match_ptr(ingenic_usb_phy_of_matches)" is
wrong
and should be replaced with ".of_match_table = ingenic_usb_phy_of_matches".
v2->v3
X1000, and X1830.
Tested-by: 周琰杰 (Zhou Yanjie)
Thanks and best regards!
On 2020/11/8 下午11:28, H. Nikolaus Schaller wrote:
Am 08.11.2020 um 16:13 schrieb Zhou Yanjie :
On 2020/11/8 下午10:35, H. Nikolaus Schaller wrote:
Am 08.11.2020 um 13:46 schrieb Zhou Yanjie :
Hello Nikolaus,
On 2020/11/8 上午3:03, H. Nikolaus Schaller wrote:
Am 07.11.2020 um 12:52 schrieb 周琰
Hi Paul,
On 2020/11/10 上午7:30, Paul Cercueil wrote:
Hi Zhou,
Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
a écrit :
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1000-Neo.
3.Add OTG/OTG
Hi Paul,
On 2020/11/10 上午7:37, Paul Cercueil wrote:
Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
a écrit :
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1000-Neo.
3.Add OTG/OTG PHY/DTRNG
Remove unnecessary "of_match_ptr()", because Ingenic SoCs all
depend on Device Tree.
Suggested-by: Paul Cercueil
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v3:
New patch.
v3->v4:
No change.
v4->v5:
Add Paul Cercue
Move Ingenic USB PHY bindings from Documentation/devicetree/bindings/usb
to Documentation/devicetree/bindings/phy, and add bindings for JZ4775 SoC
and X2000 SoC.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v8:
New patch.
.../{usb/ingenic,jz4770-phy.yaml => phy/ingenic,phy-usb.y
)
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Fix bug, ".of_match_table = of_match_ptr(ingenic_usb_phy_of_matches)" is
wrong
and should be replaced with ".of_match_table = ingenic_usb_phy_of_matches".
v2->v3
ary "platform_set_drvdata".
3.Remove the "dev" field in priv structure, and use &phy->dev instead.
v7->v8:
Add support for Ingenic JZ4775 SoC and X2000 SoC.
周琰杰 (Zhou Yanjie) (3):
USB: PHY: JZ4770: Remove unnecessary function calls.
dt-bindings: USB: A
1.Add missing nodes for Ingenic SoCs and Ingenic SoCs based boards.
2.Refresh defconfig for Ingenic SoCs based boards.
周琰杰 (Zhou Yanjie) (2):
MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
MIPS: Ingenic: Refresh defconfig for Ingenic SoCs based boards.
arch/mips/boot/dts
1.Refresh defconfig of CI20 to support OTG and RNG.
2.Refresh defconfig of CU1000-Neo to support OTG/RNG/OST/SC16IS752.
3.Refresh defconfig of CU1830-Neo to support OTG/DTRNG/OST/SC16IS752.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
arch/mips/configs/ci20_defconfig
杰 (Zhou Yanjie)
---
arch/mips/boot/dts/ingenic/ci20.dts | 16 +
arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60 +++
arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60 +++
arch/mips/boot/dts/ingenic/jz4780.dtsi| 41
Add the dmaengine bindings for the JZ4775 SoC and the X2000 SoC from Ingenic.
周琰杰 (Zhou Yanjie) (2):
dt-bindings: dmaengine: Add JZ4775 bindings.
dt-bindings: dmaengine: Add X2000 bindings.
include/dt-bindings/dma/jz4775-dma.h | 44 +
include/dt-bindings/dma
Add the dmaengine bindings for the JZ4775 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Acked-by: Rob Herring
---
include/dt-bindings/dma/jz4775-dma.h | 44
1 file changed, 44 insertions(+)
create mode 100644 include/dt-bindings/dma/jz4775-dma.h
diff
Add the dmaengine bindings for the X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Acked-by: Rob Herring
---
include/dt-bindings/dma/x2000-dma.h | 54 +
1 file changed, 54 insertions(+)
create mode 100644 include/dt-bindings/dma/x2000-dma.h
diff
Hello Nikolaus,
On 2020/11/8 上午3:03, H. Nikolaus Schaller wrote:
Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) :
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1000-Neo.
3.Add OTG/OTG PHY
Hello Nikolaus,
On 2020/11/8 上午3:05, H. Nikolaus Schaller wrote:
Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) :
1.Refresh defconfig of CI20 to support OTG and RNG.
2.Refresh defconfig of CU1000-Neo to support OTG/RNG/OST/SC16IS752.
3.Refresh defconfig of CU1830-Neo to support OTG/DTRNG/OST
On 2020/11/8 下午10:35, H. Nikolaus Schaller wrote:
Am 08.11.2020 um 13:46 schrieb Zhou Yanjie :
Hello Nikolaus,
On 2020/11/8 上午3:03, H. Nikolaus Schaller wrote:
Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) :
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG
Hello Felipe,
在 2020/7/23 下午5:19, Felipe Balbi 写道:
周琰杰 (Zhou Yanjie) writes:
1.separate the adjustments to the code style into
a separate patch.
2.Modify the help message, make it more future-proof.
3.Drop the unnecessary comment about hardware reset.
4.Create 'soc_info'
v5->v6:
1.Fix the warning that appears during compilation.
2.Used the generic PHY framework API to create the PHY,
and move the driver to driver/phy/ingenic.
周琰杰 (Zhou Yanjie) (5):
dt-bindings: USB: Add bindings for new Ingenic SoCs.
USB: PHY: JZ4770: Unify code style and simplify c
Add the USB PHY bindings for the JZ4780 SoC, the X1000 SoC and
the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
Acked-by: Rob Herring
---
Notes:
v1->v2:
Add bindings for the JZ4780 SoC.
v2->v3:
No change.
v3->v
the code.
Tested-by: 周正 (Zhou Zheng)
Suggested-by: Paul Cercueil
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v5:
New patch.
v5->v6:
No change.
drivers/usb/phy/phy-jz4770.c | 34 +++---
1 file changed, 11 insertions(+), 23 deletions(-)
diff
Add support for probing the phy-jz4770 driver on the JZ4780 SoC,
the X1000 SoC and the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add bindings for
Reformat the code (add one level of indentation before the values),
to align the code in the macro definition section.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add support
Gentle ping.
在 2020/7/1 上午12:38, 周琰杰 (Zhou Yanjie) 写道:
v2->v3:
1.Remove the wrong "WARN()".
2.Remove extra blank line.
3.Fix wrong parameters in recalc_rate/set_rate functions.
周琰杰 (Zhou Yanjie) (3):
clk: JZ4780: Add functions for enable and disable USB PHY.
clk: JZ4780:
.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/clk/ingenic/jz4780-cgu.c | 12
drivers/clk/ingenic/x1000-cgu.c | 13 +
drivers/clk/ingenic/x1830-cgu.c | 13 +
3 files changed, 38 insertions(+)
diff --git a/drivers/clk/ingenic
The "JZ4780_CLK_LCD0PIXCLK" and the "JZ4780_CLK_LCD1PIXCLK"
in the "jz4780.h" and the new added "JZ4780_CLK_EXCLK_DIV512"
in the previous patch is too long, add tabs to other lines
to align them.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie
1.Add RTC related clocks bindings for the JZ4780 SoC,
the X1000 SoC, and the X1830 SoC.
2.Add "_CLK_EXCLK_DIV512" and "_CLK_RTC" for
the JZ4780 SoC, the X1000 SoC, and the X1830 SoC.
周琰杰 (Zhou Yanjie) (3):
dt-bindings: clock: Add RTC related clocks for Ingenic
Add RTC related clocks bindings for the JZ4780 SoC, the X1000 SoC,
and the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
include/dt-bindings/clock/jz4780-cgu.h | 2 ++
include/dt-bindings/clock/x1000-cgu.h | 2 ++
include/dt-bindings/clock/x1830-cgu.h
Add the USB PHY bindings for the JZ4780 SoC, the X1000 SoC and
the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
Acked-by: Rob Herring
---
Notes:
v1->v2:
Add bindings for the JZ4780 SoC.
v2->v3:
No change.
v3->v
the code.
Tested-by: 周正 (Zhou Zheng)
Suggested-by: Paul Cercueil
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v5:
New patch.
v5->v6:
No change.
drivers/usb/phy/phy-jz4770.c | 34 +++---
1 file changed, 11 insertions(+), 23 deletions(-)
diff
v5->v6:
1.Fix the warning that appears during compilation.
2.Used the generic PHY framework API to create the PHY,
and move the driver to driver/phy/ingenic.
周琰杰 (Zhou Yanjie) (5):
dt-bindings: USB: Add bindings for new Ingenic SoCs.
USB: PHY: JZ4770: Unify code style and simplify c
Reformat the code (add one level of indentation before the values),
to align the code in the macro definition section.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add support
Add support for probing the phy-jz4770 driver on the JZ4780 SoC,
the X1000 SoC and the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add bindings for
Used the generic PHY framework API to create the PHY,
and move the driver to driver/phy/ingenic.
Tested-by: 周正 (Zhou Zheng)
Suggested-by: Felipe Balbi
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v6:
New patch
Hi Felipe,
在 2020/7/25 下午2:16, Felipe Balbi 写道:
Hi,
周琰杰 (Zhou Yanjie) writes:
Add support for probing the phy-jz4770 driver on the JZ4780 SoC,
the X1000 SoC and the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Co-developed-by: 漆鹏振 (Qi Pengzhen)
Signed-off-by: 漆鹏振 (Qi Pengzhen
Add SSI pins support for the JZ4770 SoC and the
JZ4780 SoC from Ingenic.
周琰杰 (Zhou Yanjie) (1):
pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780.
drivers/pinctrl/pinctrl-ingenic.c | 267 ++
1 file changed, 267 insertions(+)
--
2.11.0
Add SSI pins support for the JZ4770 SoC and the
JZ4780 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/pinctrl/pinctrl-ingenic.c | 267 ++
1 file changed, 267 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c
b/drivers/pinctrl
Hi Paul,
在 2020/7/23 下午4:47, Paul Cercueil 写道:
Hi Zhou,
Le jeu. 23 juil. 2020 à 15:19, 周琰杰 (Zhou Yanjie)
a écrit :
The commit 19c968222934 ("MIPS: DTS: CI20: make DM9000 Ethernet
controller use NVMEM to find the default MAC address") add EFUSE
node for DM9000 in CI20, however,
v9->v10:
Fix errors which case "make dt_binding_check" failed.
周琰杰 (Zhou Yanjie) (2):
dt-bindings: timer: Add Ingenic X1000 OST bindings.
clocksource: Ingenic: Add support for the Ingenic X1000 OST.
.../devicetree/bindings/timer/ingenic,sysost.yaml | 63 +++
drivers/clocks
Add the OST bindings for the X1 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Reviewed-by: Rob Herring
---
Notes:
v1->v2:
No change.
v2->v3:
Fix wrong parameters in "clocks".
v3-&
(Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Fix compile warnings.
Reported-by: kernel test robot
v2->v3:
No change.
v3->v4:
1.Rename "ost" to "sysost"
1.Remove unrelated changes.
2.Remove ost_clock_
v6->v7:
1.Remove "default MACH_INGENIC" and make option silent.
2.Enable the corresponding driver in the platform's Kconfig.
3.Update DT of X1000 and X1830, use SYSOST instead of TCU
to provide clocksource and clockevent.
周琰杰 (Zhou Yanjie) (5):
dt-bindings: timer: Add
The previous clocksource patch in this series ([2/3]) has remove
"default MACH_INGENIC" and make option silent, so we need to
enable the corresponding driver in the platform's Kconfig.
Suggested-by: Daniel Lezcano
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
this series of patches, which can provide 32bit timing
length, so use SYSOST instead of TCU to provide clocksource
and clockevent to solve the aforementioned problems.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v7:
New patch.
arch/mips/boot/dts/ingenic/cu1830
(Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Fix compile warnings.
Reported-by: kernel test robot
v2->v3:
No change.
v3->v4:
1.Rename "ost" to "sysost"
1.Remove unrelated changes.
2.Remove ost_clock_
Add the OST bindings for the X1 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Reviewed-by: Rob Herring
---
Notes:
No change.
v2->v3:
Fix wrong parameters in "clocks".
v3->v4:
1
this series of patches, which can provide 32bit timing
length, so use SYSOST instead of TCU to provide clocksource
and clockevent to solve the aforementioned problems.
Tested-by: 周正 (Zhou Zheng)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v7:
New patch.
arch/mips/boot/dts/ingenic/cu1000
Hi Sergei,
在 2020/7/18 下午4:39, Sergei Shtylyov 写道:
Hello!
On 17.07.2020 19:59, 周琰杰 (Zhou Yanjie) wrote:
The previous clocksource patch in this series ([2/3]) has remove
Removed.
"default MACH_INGENIC" and make option silent, so we need to
Made?
enable the corresponding
Hello Paul and Daniel,
在 2020/7/18 下午9:12, Paul Cercueil 写道:
Hi Daniel,
Le ven. 17 juil. 2020 à 10:02, Daniel Lezcano
a écrit :
On 17/07/2020 08:13, Zhou Yanjie wrote:
Hi Daniel,
在 2020/7/17 下午12:20, Daniel Lezcano 写道:
On 10/07/2020 19:02, 周琰杰 (Zhou Yanjie) wrote:
X1000 and SoCs
Hi Paul,
在 2020/7/18 下午11:44, Paul Cercueil 写道:
Hi Zhou,
Le sam. 18 juil. 2020 à 21:42, Zhou Yanjie
a écrit :
Hello Paul and Daniel,
在 2020/7/18 下午9:12, Paul Cercueil 写道:
Hi Daniel,
Le ven. 17 juil. 2020 à 10:02, Daniel Lezcano
a écrit :
On 17/07/2020 08:13, Zhou Yanjie wrote:
Hi
在 2020/7/19 上午12:11, Paul Cercueil 写道:
Le sam. 18 juil. 2020 à 23:55, Zhou Yanjie
a écrit :
Hi Paul,
在 2020/7/18 下午11:44, Paul Cercueil 写道:
Hi Zhou,
Le sam. 18 juil. 2020 à 21:42, Zhou Yanjie
a écrit :
Hello Paul and Daniel,
在 2020/7/18 下午9:12, Paul Cercueil 写道:
Hi Daniel,
Le
(Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Fix compile warnings.
Reported-by: kernel test robot
v2->v3:
No change.
v3->v4:
1.Rename "ost" to "sysost"
1.Remove unrelated changes.
2.Remove ost_clock_
v7->v8:
Revert the changes made in v7, remove the "default MACH_INGENIC"
in SYSOST, and modify the bool description in OST to make it
consistent with the style of TCU and SYSOST.
周琰杰 (Zhou Yanjie) (2):
dt-bindings: timer: Add Ingenic X1000 OST bindings.
clocksource: Ingenic: Ad
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